>>> yosys: Building testing/yosys 0.57-r0 (using abuild 3.16.0_rc4-r0) started Fri, 24 Oct 2025 21:42:34 +0000 >>> yosys: Validating /home/buildozer/aports/testing/yosys/APKBUILD... >>> yosys: Analyzing dependencies... >>> yosys: Installing for build: build-base abc bash bison boost-dev flex-dev gawk graphviz-dev libffi-dev lld protobuf-dev python3 readline-dev tcl-dev zlib-dev gtkwave iverilog ( 1/352) Installing abc (0_git20240102-r0) ( 2/352) Installing bash (5.3.3-r1) bash-5.3.3-r1.post-install: Executing script... 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install icu-data-en-76.1-r1.post-install: * package icu-data-full. icu-data-en-76.1-r1.post-install: * ( 20/352) Installing icu-libs (76.1-r1) ( 21/352) Installing boost1.84-locale (1.84.0-r3) ( 22/352) Installing boost1.84-log (1.84.0-r3) ( 23/352) Installing boost1.84-log_setup (1.84.0-r3) ( 24/352) Installing boost1.84-math (1.84.0-r3) ( 25/352) Installing boost1.84-prg_exec_monitor (1.84.0-r3) ( 26/352) Installing boost1.84-program_options (1.84.0-r3) ( 27/352) Installing libffi (3.5.2-r0) ( 28/352) Installing gdbm (1.26-r0) ( 29/352) Installing mpdecimal (4.0.1-r0) ( 30/352) Installing libpanelw (6.5_p20251010-r0) ( 31/352) Installing sqlite-libs (3.50.4-r1) ( 32/352) Installing python3 (3.12.12-r0) ( 33/352) Installing python3-pycache-pyc0 (3.12.12-r0) ( 34/352) Installing pyc (3.12.12-r0) ( 35/352) Installing python3-pyc (3.12.12-r0) ( 36/352) Installing boost1.84-python3 (1.84.0-r3) ( 37/352) Installing boost1.84-random (1.84.0-r3) ( 38/352) Installing boost1.84-regex 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Executing script... gdk-pixbuf-2.44.4-r0.trigger: Executing script... gtk-update-icon-cache-3.24.51-r0.trigger: Executing script... gtk+3.0-3.24.51-r0.trigger: Executing script... OK: 1085 MiB in 459 packages >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Cleaning up tmpdir >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.57.tar.gz Connecting to distfiles.alpinelinux.org (172.105.82.32:443) wget: server returned error: HTTP/1.1 404 Not Found >>> yosys: Fetching yosys-0.57.tar.gz::https://github.com/YosysHQ/yosys/releases/download/v0.57/yosys.tar.gz Connecting to github.com (140.82.121.3:443) Connecting to release-assets.githubusercontent.com (185.199.108.133:443) saving to '/var/cache/distfiles/edge/yosys-0.57.tar.gz.part' yosys-0.57.tar.gz.pa 100% |********************************| 10.1M 0:00:00 ETA '/var/cache/distfiles/edge/yosys-0.57.tar.gz.part' saved /var/cache/distfiles/edge/yosys-0.57.tar.gz: OK >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.57.tar.gz /var/cache/distfiles/edge/yosys-0.57.tar.gz: OK >>> yosys: Unpacking /var/cache/distfiles/edge/yosys-0.57.tar.gz... [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] ENABLE_ABC:=1 [ 0%] Building kernel/version_3aca86049e79a165932e3e7660358376f45acaed.cc [ 0%] Building kernel/celltypes.pyh [ 0%] Building kernel/consteval.pyh [ 0%] Building kernel/log.pyh [ 0%] Building kernel/register.pyh [ 0%] Building kernel/rtlil.pyh [ 0%] Building kernel/sigtools.pyh [ 0%] Building kernel/yosys.pyh [ 0%] Building kernel/cost.pyh [ 0%] Building kernel/driver.o [ 0%] Building techlibs/common/simlib_help.inc [ 0%] Building techlibs/common/simcells_help.inc [ 1%] Building kernel/rtlil.o [ 1%] Building kernel/log.o [ 1%] Building kernel/calc.o [ 2%] Building kernel/yosys.o [ 2%] Building kernel/io.o [ 2%] Building kernel/gzip.o [ 3%] Building kernel/log_help.o [ 3%] Building kernel/binding.o [ 3%] Building kernel/tclapi.o [ 3%] Building kernel/cellaigs.o [ 4%] Building kernel/celledges.o [ 4%] Building kernel/cost.o [ 4%] Building kernel/satgen.o [ 4%] Building kernel/scopeinfo.o [ 5%] Building kernel/qcsat.o [ 5%] Building kernel/mem.o [ 5%] Building kernel/ffmerge.o [ 6%] Building kernel/ff.o [ 6%] Building kernel/yw.o [ 6%] Building kernel/json.o [ 6%] Building kernel/fmt.o [ 7%] Building kernel/sexpr.o [ 7%] Building kernel/drivertools.o [ 7%] Building kernel/functional.o [ 7%] Building kernel/fstdata.o [ 8%] Building libs/bigint/BigIntegerAlgorithms.o [ 8%] Building libs/bigint/BigInteger.o [ 8%] Building libs/bigint/BigIntegerUtils.o [ 9%] Building libs/bigint/BigUnsigned.o [ 9%] Building libs/bigint/BigUnsignedInABase.o [ 9%] Building libs/sha1/sha1.o [ 9%] Building libs/json11/json11.o [ 10%] Building libs/ezsat/ezsat.o [ 10%] Building libs/ezsat/ezminisat.o [ 10%] Building libs/minisat/Options.o [ 10%] Building libs/minisat/SimpSolver.o [ 11%] Building libs/minisat/Solver.o [ 11%] Building libs/minisat/System.o [ 11%] Building libs/fst/fstapi.o [ 12%] Building libs/fst/fastlz.o [ 12%] Building libs/fst/lz4.o [ 12%] Building libs/subcircuit/subcircuit.o [ 12%] Building frontends/aiger/aigerparse.o [ 13%] Building frontends/aiger2/xaiger.o [ 13%] Building frontends/ast/ast.o [ 13%] Building frontends/ast/simplify.o [ 13%] Building frontends/ast/genrtlil.o [ 14%] Building frontends/ast/dpicall.o [ 14%] Building frontends/ast/ast_binding.o In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:125:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' 125 | capacity(size); | ~~~~~~~~^~~~~~ libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]' 48 | void reserve(K key) { map.growTo(index(key)+1); } | ~~~~~~~~~~^~~~~~~~~~~~~~ libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]' 338 | void init (const K& idx){ occs.reserve(idx); occs[idx].clear(); dirty.reserve(idx, 0); } | ~~~~~~~~~~~~^~~~~ libs/minisat/Solver.cc:134:19: required from here 134 | watches .init(mkLit(v, false)); | ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:107:35: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 107 | ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:125:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' 125 | capacity(size); | ~~~~~~~~^~~~~~ libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]' 48 | void reserve(K key) { map.growTo(index(key)+1); } | ~~~~~~~~~~^~~~~~~~~~~~~~ libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]' 338 | void init (const K& idx){ occs.reserve(idx); occs[idx].clear(); dirty.reserve(idx, 0); } | ~~~~~~~~~~~~^~~~~ libs/minisat/SimpSolver.cc:92:26: required from here 92 | occurs .init (v); | ~~~~~~~~~~~~~~~~~^~~ libs/minisat/Vec.h:107:35: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 107 | ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 14%] Building frontends/blif/blifparse.o [ 15%] Building frontends/json/jsonparse.o [ 15%] Building frontends/liberty/liberty.o [ 15%] Building frontends/rpc/rpc_frontend.o [ 15%] Building frontends/rtlil/rtlil_parser.tab.cc [ 15%] Building frontends/rtlil/rtlil_lexer.cc [ 16%] Building frontends/rtlil/rtlil_frontend.o [ 16%] Building frontends/verific/verific.o [ 16%] Building frontends/verilog/verilog_parser.tab.cc kernel/fmt.cc: In member function 'std::string Yosys::Fmt::render() const': kernel/fmt.cc:808:78: warning: left operand of comma operator has no effect [-Wunused-value] 808 | buf += (part.hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[subvalue.as_int()]; | ~~~~~^~~~~~~~~ [ 18%] Building frontends/verilog/verilog_error.o [ 18%] Building frontends/verilog/const2ast.o [ 18%] Building passes/cmds/exec.o [ 18%] Building passes/cmds/add.o [ 19%] Building passes/cmds/delete.o [ 19%] Building passes/cmds/design.o [ 19%] Building passes/cmds/select.o [ 19%] Building passes/cmds/show.o [ 20%] Building passes/cmds/viz.o [ 20%] Building passes/cmds/rename.o [ 20%] Building passes/cmds/autoname.o [ 21%] Building passes/cmds/connect.o [ 21%] Building passes/cmds/scatter.o [ 21%] Building passes/cmds/setundef.o [ 21%] Building passes/cmds/splitnets.o [ 22%] Building passes/cmds/splitcells.o [ 22%] Building passes/cmds/stat.o [ 22%] Building passes/cmds/internal_stats.o [ 22%] Building passes/cmds/setattr.o In file included from /usr/include/c++/15.2.0/x86_64-alpine-linux-musl/bits/c++allocator.h:33, from /usr/include/c++/15.2.0/bits/allocator.h:46, from /usr/include/c++/15.2.0/bits/stl_tree.h:66, from /usr/include/c++/15.2.0/map:64, from ./kernel/yosys_common.h:24, from ./kernel/rtlil.h:23, from ./kernel/drivertools.h:25, from kernel/drivertools.cc:20: In member function 'void std::__new_allocator<_Tp>::construct(_Up*, _Args&& ...) [with _Up = Yosys::RTLIL::State; _Args = {const Yosys::RTLIL::State&}; _Tp = Yosys::RTLIL::State]', inlined from 'static void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::RTLIL::State; _Args = {const Yosys::RTLIL::State&}; _Tp = Yosys::RTLIL::State]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:674:17, inlined from 'void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {const Yosys::RTLIL::State&}; _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1427:21, inlined from 'bool Yosys::DriveChunkMultiple::try_append(const Yosys::DriveBitMultiple&)' at kernel/drivertools.cc:263:39, inlined from 'bool Yosys::DriveChunkMultiple::try_append(const Yosys::DriveBitMultiple&)' at kernel/drivertools.cc:247:6: /usr/include/c++/15.2.0/bits/new_allocator.h:191:11: warning: 'constant' may be used uninitialized [-Wmaybe-uninitialized] 191 | { ::new((void *)__p) _Up(std::forward<_Args>(__args)...); } | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/drivertools.cc: In member function 'bool Yosys::DriveChunkMultiple::try_append(const Yosys::DriveBitMultiple&)': kernel/drivertools.cc:252:15: note: 'constant' was declared here 252 | State constant; | ^~~~~~~~ [ 23%] Building passes/cmds/copy.o [ 23%] Building passes/cmds/splice.o [ 23%] Building passes/cmds/scc.o [ 24%] Building passes/cmds/glift.o [ 24%] Building passes/cmds/torder.o [ 24%] Building passes/cmds/logcmd.o [ 24%] Building passes/cmds/tee.o [ 25%] Building passes/cmds/write_file.o [ 25%] Building passes/cmds/connwrappers.o [ 25%] Building passes/cmds/cover.o [ 25%] Building passes/cmds/trace.o [ 26%] Building passes/cmds/plugin.o [ 26%] Building passes/cmds/check.o [ 26%] Building passes/cmds/edgetypes.o [ 27%] Building passes/cmds/portlist.o [ 27%] Building passes/cmds/chformal.o [ 27%] Building passes/cmds/chtype.o [ 27%] Building passes/cmds/blackbox.o [ 28%] Building passes/cmds/ltp.o [ 28%] Building passes/cmds/bugpoint.o [ 28%] Building passes/cmds/scratchpad.o [ 28%] Building passes/cmds/logger.o [ 29%] Building passes/cmds/printattrs.o [ 29%] Building passes/cmds/sta.o [ 29%] Building passes/cmds/clean_zerowidth.o [ 30%] Building passes/cmds/xprop.o [ 30%] Building passes/cmds/dft_tag.o [ 30%] Building passes/cmds/future.o [ 30%] Building passes/cmds/box_derive.o [ 31%] Building passes/cmds/example_dt.o [ 31%] Building passes/cmds/portarcs.o [ 31%] Building passes/cmds/wrapcell.o [ 32%] Building passes/cmds/setenv.o [ 32%] Building passes/cmds/abstract.o [ 32%] Building passes/cmds/test_select.o [ 32%] Building passes/cmds/timeest.o [ 33%] Building passes/cmds/linecoverage.o [ 33%] Building passes/equiv/equiv_make.o [ 33%] Building passes/equiv/equiv_miter.o [ 33%] Building passes/equiv/equiv_simple.o [ 34%] Building passes/equiv/equiv_status.o [ 34%] Building passes/equiv/equiv_add.o [ 34%] Building passes/equiv/equiv_remove.o [ 35%] Building passes/equiv/equiv_induct.o In file included from ./kernel/yosys.h:42, from passes/cmds/abstract.cc:1: passes/cmds/abstract.cc: In member function 'virtual void {anonymous}::AbstractPass::execute(std::vector >, Yosys::RTLIL::Design*)': ./kernel/log.h:227:77: warning: this statement may fall through [-Wimplicit-fallthrough=] 227 | # define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__) passes/cmds/abstract.cc:471:41: note: in expansion of macro 'log_assert' 471 | log_assert(false); | ^~~~~~~~~~ passes/cmds/abstract.cc:472:33: note: here 472 | case Enable::ActiveLow: | ^~~~ [ 35%] Building passes/equiv/equiv_struct.o [ 35%] Building passes/equiv/equiv_purge.o [ 35%] Building passes/equiv/equiv_mark.o [ 36%] Building passes/equiv/equiv_opt.o [ 36%] Building passes/fsm/fsm.o [ 36%] Building passes/fsm/fsm_detect.o [ 36%] Building passes/fsm/fsm_extract.o [ 37%] Building passes/fsm/fsm_opt.o [ 37%] Building passes/fsm/fsm_expand.o [ 37%] Building passes/fsm/fsm_recode.o [ 38%] Building passes/fsm/fsm_info.o [ 38%] Building passes/fsm/fsm_export.o [ 38%] Building passes/fsm/fsm_map.o [ 38%] Building passes/hierarchy/flatten.o [ 39%] Building passes/hierarchy/hierarchy.o [ 39%] Building passes/hierarchy/uniquify.o [ 39%] Building passes/hierarchy/submod.o [ 39%] Building passes/hierarchy/keep_hierarchy.o [ 40%] Building passes/memory/memory.o [ 40%] Building passes/memory/memory_dff.o [ 40%] Building passes/memory/memory_share.o [ 41%] Building passes/memory/memory_collect.o [ 41%] Building passes/memory/memory_unpack.o [ 41%] Building passes/memory/memory_bram.o [ 41%] Building passes/memory/memory_map.o [ 42%] Building passes/memory/memory_memx.o [ 42%] Building passes/memory/memory_nordff.o [ 42%] Building passes/memory/memory_narrow.o [ 42%] Building passes/memory/memory_libmap.o [ 43%] Building passes/memory/memory_bmux2rom.o [ 43%] Building passes/memory/memlib.o [ 43%] Building passes/opt/opt.o [ 44%] Building passes/opt/opt_merge.o [ 44%] Building passes/opt/opt_mem.o [ 44%] Building passes/opt/opt_mem_feedback.o [ 44%] Building passes/opt/opt_mem_priority.o [ 45%] Building passes/opt/opt_mem_widen.o [ 45%] Building passes/opt/opt_muxtree.o [ 45%] Building passes/opt/opt_reduce.o [ 45%] Building passes/opt/opt_dff.o [ 46%] Building passes/opt/opt_share.o [ 46%] Building passes/opt/opt_clean.o [ 46%] Building passes/opt/opt_expr.o [ 47%] Building passes/opt/opt_hier.o [ 47%] Building passes/opt/share.o [ 47%] Building passes/opt/wreduce.o [ 47%] Building passes/opt/opt_demorgan.o [ 48%] Building passes/opt/rmports.o [ 48%] Building passes/opt/opt_lut.o [ 48%] Building passes/opt/opt_lut_ins.o [ 48%] Building passes/opt/opt_ffinv.o [ 49%] Building passes/opt/pmux2shiftx.o [ 49%] Building passes/opt/muxpack.o [ 49%] Building passes/opt/peepopt_pm.h [ 49%] Building passes/pmgen/test_pmgen_pm.h [ 49%] Building techlibs/ice40/ice40_dsp_pm.h [ 49%] Building techlibs/xilinx/xilinx_srl_pm.h [ 50%] Building passes/proc/proc.o [ 50%] Building passes/proc/proc_prune.o [ 50%] Building passes/proc/proc_clean.o [ 51%] Building passes/proc/proc_rmdead.o [ 51%] Building passes/proc/proc_init.o [ 51%] Building passes/proc/proc_arst.o [ 51%] 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Building share/gatemate/lut_tree_map.v [ 99%] Building share/quicklogic/qlf_k6n10f/bram_types_sim.v [ 99%] Building frontends/verilog/verilog_lexer.o [ 99%] Building yosys-filterlib [ 99%] Building kernel/python_wrappers.o kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::IdString::in_(boost::python::list)': kernel/python_wrappers.cc:5475:52: warning: 'bool Yosys::RTLIL::IdString::in(const Yosys::hashlib::pool&) const' is deprecated [-Wdeprecated-declarations] 5475 | bool ret_ = this->get_cpp_obj()->in(rhs___tmp); | ~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ In file included from ./kernel/yosys.h:43, from ./kernel/celltypes.h:23, from kernel/python_wrappers.cc:22: ./kernel/rtlil.h:448:13: note: declared here 448 | inline bool RTLIL::IdString::in(const pool &rhs) const { return rhs.count(*this) != 0; } | ^~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::AttrObject::get_blackbox_attribute() const': kernel/python_wrappers.cc:5862:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 5862 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::AttrObject::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:5869:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 5869 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::NamedObject::get_blackbox_attribute() const': kernel/python_wrappers.cc:6006:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6006 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::NamedObject::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:6013:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6013 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::CaseRule::get_blackbox_attribute() const': kernel/python_wrappers.cc:6473:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6473 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::CaseRule::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:6480:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6480 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::SwitchRule::get_blackbox_attribute() const': kernel/python_wrappers.cc:6653:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6653 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::SwitchRule::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:6660:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6660 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Process::get_blackbox_attribute() const': kernel/python_wrappers.cc:6905:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6905 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Process::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:6912:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 6912 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Cell::get_blackbox_attribute() const': kernel/python_wrappers.cc:8189:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 8189 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Cell::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:8196:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 8196 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Wire::get_blackbox_attribute() const': kernel/python_wrappers.cc:8457:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 8457 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Wire::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:8464:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 8464 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Memory::get_blackbox_attribute() const': kernel/python_wrappers.cc:8647:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 8647 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'bool YOSYS_PYTHON::Memory::get_blackbox_attribute(bool) const': kernel/python_wrappers.cc:8654:72: warning: 'bool Yosys::RTLIL::AttrObject::get_blackbox_attribute(bool) const' is deprecated: Use Module::get_blackbox_attribute() instead. [-Wdeprecated-declarations] 8654 | bool ret_ = this->get_cpp_obj()->get_blackbox_attribute(ignore_wb); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ ./kernel/rtlil.h:894:14: note: declared here 894 | bool get_blackbox_attribute(bool ignore_wb=false) const { | ^~~~~~~~~~~~~~~~~~~~~~ kernel/python_wrappers.cc: In member function 'boost::python::list YOSYS_PYTHON::Design::selected_whole_modules() const': kernel/python_wrappers.cc:13033:112: warning: 'std::vector Yosys::RTLIL::Design::selected_whole_modules() const' is deprecated: Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers. [-Wdeprecated-declarations] 13033 | std::vector ret_ = this->get_cpp_obj()->selected_whole_modules(); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ ./kernel/rtlil.h:1466:37: note: declared here 1466 | std::vector selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); } | ^~~~~~~~~~~~~~~~~~~~~~ kernel/register.cc: In constructor 'Yosys::CellHelpMessages::CellHelpMessages()': kernel/register.cc:715:9: note: variable tracking size limit exceeded with '-fvar-tracking-assignments', retrying without 715 | CellHelpMessages() { | ^~~~~~~~~~~~~~~~ In file included from /usr/include/c++/15.2.0/string:56, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40: In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_hdump(boost::python::dict)' at kernel/python_wrappers.cc:14027:74: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_hdump(boost::python::dict)': kernel/python_wrappers.cc:14027:102: note: '' declared here 14027 | string tmp_263 = boost::python::extract(val_tmp_261[cntr_262]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_hdump(boost::python::dict)' at kernel/python_wrappers.cc:14027:74: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_hdump(boost::python::dict)': kernel/python_wrappers.cc:14027:102: note: '' declared here 14027 | string tmp_263 = boost::python::extract(val_tmp_261[cntr_262]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_hdump(boost::python::dict)' at kernel/python_wrappers.cc:14022:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_hdump(boost::python::dict)': kernel/python_wrappers.cc:14022:100: note: '' declared here 14022 | string key_tmp_261 = boost::python::extract(rhs_keylist[ cntr_260 ]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_yosys_output_files(boost::python::list)' at kernel/python_wrappers.cc:14376:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_yosys_output_files(boost::python::list)': kernel/python_wrappers.cc:14376:86: note: '' declared here 14376 | string tmp_287 = boost::python::extract(rhs[cntr_286]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_yosys_output_files(boost::python::list)' at kernel/python_wrappers.cc:14376:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_yosys_output_files(boost::python::list)': kernel/python_wrappers.cc:14376:86: note: '' declared here 14376 | string tmp_287 = boost::python::extract(rhs[cntr_286]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_yosys_input_files(boost::python::list)' at kernel/python_wrappers.cc:14354:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_yosys_input_files(boost::python::list)': kernel/python_wrappers.cc:14354:86: note: '' declared here 14354 | string tmp_284 = boost::python::extract(rhs[cntr_283]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_yosys_input_files(boost::python::list)' at kernel/python_wrappers.cc:14354:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_yosys_input_files(boost::python::list)': kernel/python_wrappers.cc:14354:86: note: '' declared here 14354 | string tmp_284 = boost::python::extract(rhs[cntr_283]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_experimentals_ignored(boost::python::list)' at kernel/python_wrappers.cc:14096:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_experimentals_ignored(boost::python::list)': kernel/python_wrappers.cc:14096:86: note: '' declared here 14096 | string tmp_272 = boost::python::extract(rhs[cntr_271]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_experimentals_ignored(boost::python::list)' at kernel/python_wrappers.cc:14096:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_experimentals_ignored(boost::python::list)': kernel/python_wrappers.cc:14096:86: note: '' declared here 14096 | string tmp_272 = boost::python::extract(rhs[cntr_271]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_experimentals(boost::python::list)' at kernel/python_wrappers.cc:14074:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_experimentals(boost::python::list)': kernel/python_wrappers.cc:14074:86: note: '' declared here 14074 | string tmp_269 = boost::python::extract(rhs[cntr_268]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_experimentals(boost::python::list)' at kernel/python_wrappers.cc:14074:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_experimentals(boost::python::list)': kernel/python_wrappers.cc:14074:86: note: '' declared here 14074 | string tmp_269 = boost::python::extract(rhs[cntr_268]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_warnings(boost::python::list)' at kernel/python_wrappers.cc:14052:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_warnings(boost::python::list)': kernel/python_wrappers.cc:14052:86: note: '' declared here 14052 | string tmp_266 = boost::python::extract(rhs[cntr_265]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_warnings(boost::python::list)' at kernel/python_wrappers.cc:14052:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_warnings(boost::python::list)': kernel/python_wrappers.cc:14052:86: note: '' declared here 14052 | string tmp_266 = boost::python::extract(rhs[cntr_265]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::cmd_log_args(boost::python::list)' at kernel/python_wrappers.cc:5108:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::cmd_log_args(boost::python::list)': kernel/python_wrappers.cc:5108:85: note: '' declared here 5108 | string tmp_33 = boost::python::extract(args[cntr_32]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::cmd_log_args(boost::python::list)' at kernel/python_wrappers.cc:5108:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::cmd_log_args(boost::python::list)': kernel/python_wrappers.cc:5108:85: note: '' declared here 5108 | string tmp_33 = boost::python::extract(args[cntr_32]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::cmd_error(boost::python::list, size_t, std::string)' at kernel/python_wrappers.cc:5120:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::cmd_error(boost::python::list, size_t, std::string)': kernel/python_wrappers.cc:5120:85: note: '' declared here 5120 | string tmp_35 = boost::python::extract(args[cntr_34]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::cmd_error(boost::python::list, size_t, std::string)' at kernel/python_wrappers.cc:5120:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::cmd_error(boost::python::list, size_t, std::string)': kernel/python_wrappers.cc:5120:85: note: '' declared here 5120 | string tmp_35 = boost::python::extract(args[cntr_34]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_scratchpads(boost::python::list)' at kernel/python_wrappers.cc:13993:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_scratchpads(boost::python::list)': kernel/python_wrappers.cc:13993:86: note: '' declared here 13993 | string tmp_257 = boost::python::extract(rhs[cntr_256]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_log_scratchpads(boost::python::list)' at kernel/python_wrappers.cc:13993:65: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_log_scratchpads(boost::python::list)': kernel/python_wrappers.cc:13993:86: note: '' declared here 13993 | string tmp_257 = boost::python::extract(rhs[cntr_256]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::load_plugin(std::string, boost::python::list)' at kernel/python_wrappers.cc:13960:69: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::load_plugin(std::string, boost::python::list)': kernel/python_wrappers.cc:13960:90: note: '' declared here 13960 | string tmp_254 = boost::python::extract(aliases[cntr_253]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::load_plugin(std::string, boost::python::list)' at kernel/python_wrappers.cc:13960:69: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::load_plugin(std::string, boost::python::list)': kernel/python_wrappers.cc:13960:90: note: '' declared here 13960 | string tmp_254 = boost::python::extract(aliases[cntr_253]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'static void YOSYS_PYTHON::Pass::call__YOSYS_NAMESPACE_RTLIL_Design__std_vector_string_(YOSYS_PYTHON::Design*, boost::python::list)' at kernel/python_wrappers.cc:5162:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In static member function 'static void YOSYS_PYTHON::Pass::call__YOSYS_NAMESPACE_RTLIL_Design__std_vector_string_(YOSYS_PYTHON::Design*, boost::python::list)': kernel/python_wrappers.cc:5162:85: note: '' declared here 5162 | string tmp_41 = boost::python::extract(args[cntr_40]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'static void YOSYS_PYTHON::Pass::call__YOSYS_NAMESPACE_RTLIL_Design__std_vector_string_(YOSYS_PYTHON::Design*, boost::python::list)' at kernel/python_wrappers.cc:5162:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In static member function 'static void YOSYS_PYTHON::Pass::call__YOSYS_NAMESPACE_RTLIL_Design__std_vector_string_(YOSYS_PYTHON::Design*, boost::python::list)': kernel/python_wrappers.cc:5162:85: note: '' declared here 5162 | string tmp_41 = boost::python::extract(args[cntr_40]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'static void YOSYS_PYTHON::Pass::call_on_selection__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Selection__std_vector_string_(YOSYS_PYTHON::Design*, const YOSYS_PYTHON::Selection*, boost::python::list)' at kernel/python_wrappers.cc:5180:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In static member function 'static void YOSYS_PYTHON::Pass::call_on_selection__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Selection__std_vector_string_(YOSYS_PYTHON::Design*, const YOSYS_PYTHON::Selection*, boost::python::list)': kernel/python_wrappers.cc:5180:85: note: '' declared here 5180 | string tmp_43 = boost::python::extract(args[cntr_42]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'static void YOSYS_PYTHON::Pass::call_on_selection__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Selection__std_vector_string_(YOSYS_PYTHON::Design*, const YOSYS_PYTHON::Selection*, boost::python::list)' at kernel/python_wrappers.cc:5180:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In static member function 'static void YOSYS_PYTHON::Pass::call_on_selection__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Selection__std_vector_string_(YOSYS_PYTHON::Design*, const YOSYS_PYTHON::Selection*, boost::python::list)': kernel/python_wrappers.cc:5180:85: note: '' declared here 5180 | string tmp_43 = boost::python::extract(args[cntr_42]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design(boost::python::list, size_t, YOSYS_PYTHON::Design*)' at kernel/python_wrappers.cc:5132:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design(boost::python::list, size_t, YOSYS_PYTHON::Design*)': kernel/python_wrappers.cc:5132:85: note: '' declared here 5132 | string tmp_37 = boost::python::extract(args[cntr_36]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design(boost::python::list, size_t, YOSYS_PYTHON::Design*)' at kernel/python_wrappers.cc:5132:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design(boost::python::list, size_t, YOSYS_PYTHON::Design*)': kernel/python_wrappers.cc:5132:85: note: '' declared here 5132 | string tmp_37 = boost::python::extract(args[cntr_36]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design__bool(boost::python::list, size_t, YOSYS_PYTHON::Design*, bool)' at kernel/python_wrappers.cc:5144:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design__bool(boost::python::list, size_t, YOSYS_PYTHON::Design*, bool)': kernel/python_wrappers.cc:5144:85: note: '' declared here 5144 | string tmp_39 = boost::python::extract(args[cntr_38]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design__bool(boost::python::list, size_t, YOSYS_PYTHON::Design*, bool)' at kernel/python_wrappers.cc:5144:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Pass::extra_args__std_vector_string___size_t__YOSYS_NAMESPACE_RTLIL_Design__bool(boost::python::list, size_t, YOSYS_PYTHON::Design*, bool)': kernel/python_wrappers.cc:5144:85: note: '' declared here 5144 | string tmp_39 = boost::python::extract(args[cntr_38]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'static void YOSYS_PYTHON::Pass::call_on_module__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Module__std_vector_string_(YOSYS_PYTHON::Design*, YOSYS_PYTHON::Module*, boost::python::list)' at kernel/python_wrappers.cc:5198:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In static member function 'static void YOSYS_PYTHON::Pass::call_on_module__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Module__std_vector_string_(YOSYS_PYTHON::Design*, YOSYS_PYTHON::Module*, boost::python::list)': kernel/python_wrappers.cc:5198:85: note: '' declared here 5198 | string tmp_45 = boost::python::extract(args[cntr_44]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'static void YOSYS_PYTHON::Pass::call_on_module__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Module__std_vector_string_(YOSYS_PYTHON::Design*, YOSYS_PYTHON::Module*, boost::python::list)' at kernel/python_wrappers.cc:5198:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In static member function 'static void YOSYS_PYTHON::Pass::call_on_module__YOSYS_NAMESPACE_RTLIL_Design__YOSYS_NAMESPACE_RTLIL_Module__std_vector_string_(YOSYS_PYTHON::Design*, YOSYS_PYTHON::Module*, boost::python::list)': kernel/python_wrappers.cc:5198:85: note: '' declared here 5198 | string tmp_45 = boost::python::extract(args[cntr_44]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_pass_register(boost::python::dict)' at kernel/python_wrappers.cc:14292:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_pass_register(boost::python::dict)': kernel/python_wrappers.cc:14292:100: note: '' declared here 14292 | string key_tmp_278 = boost::python::extract(rhs_keylist[ cntr_277 ]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_saved_designs(boost::python::dict)' at kernel/python_wrappers.cc:14405:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_saved_designs(boost::python::dict)': kernel/python_wrappers.cc:14405:100: note: '' declared here 14405 | string key_tmp_290 = boost::python::extract(rhs_keylist[ cntr_289 ]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_loaded_plugin_aliases(boost::python::dict)' at kernel/python_wrappers.cc:14453:84: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_loaded_plugin_aliases(boost::python::dict)': kernel/python_wrappers.cc:14453:105: note: '' declared here 14453 | string val_tmp_296 = boost::python::extract(rhs[rhs_keylist[ cntr_295 ]]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_loaded_plugin_aliases(boost::python::dict)' at kernel/python_wrappers.cc:14452:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_loaded_plugin_aliases(boost::python::dict)': kernel/python_wrappers.cc:14452:100: note: '' declared here 14452 | string key_tmp_296 = boost::python::extract(rhs_keylist[ cntr_295 ]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_extra_coverage_data(boost::python::dict)' at kernel/python_wrappers.cc:14266:78: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_extra_coverage_data(boost::python::dict)': kernel/python_wrappers.cc:14266:99: note: '' declared here 14266 | string val_tmp_275___tmp_0 = boost::python::extract(val_tmp_275[0]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_extra_coverage_data(boost::python::dict)' at kernel/python_wrappers.cc:14264:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_extra_coverage_data(boost::python::dict)': kernel/python_wrappers.cc:14264:100: note: '' declared here 14264 | string key_tmp_275 = boost::python::extract(rhs_keylist[ cntr_274 ]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Module::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:12576:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Module::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:12576:87: note: '' declared here 12576 | string tmp_224 = boost::python::extract(data[cntr_223]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Module::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:12576:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Module::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:12576:87: note: '' declared here 12576 | string tmp_224 = boost::python::extract(data[cntr_223]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Module::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:12564:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Module::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:12564:87: note: '' declared here 12564 | string tmp_222 = boost::python::extract(data[cntr_221]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Module::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:12564:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Module::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:12564:87: note: '' declared here 12564 | string tmp_222 = boost::python::extract(data[cntr_221]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Memory::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8689:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Memory::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8689:87: note: '' declared here 8689 | string tmp_176 = boost::python::extract(data[cntr_175]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Memory::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8689:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Memory::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8689:87: note: '' declared here 8689 | string tmp_176 = boost::python::extract(data[cntr_175]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Memory::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8677:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Memory::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8677:87: note: '' declared here 8677 | string tmp_174 = boost::python::extract(data[cntr_173]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Memory::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8677:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Memory::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8677:87: note: '' declared here 8677 | string tmp_174 = boost::python::extract(data[cntr_173]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Wire::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8499:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Wire::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8499:87: note: '' declared here 8499 | string tmp_167 = boost::python::extract(data[cntr_166]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Wire::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8499:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Wire::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8499:87: note: '' declared here 8499 | string tmp_167 = boost::python::extract(data[cntr_166]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Wire::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8487:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Wire::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8487:87: note: '' declared here 8487 | string tmp_165 = boost::python::extract(data[cntr_164]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Wire::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8487:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Wire::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8487:87: note: '' declared here 8487 | string tmp_165 = boost::python::extract(data[cntr_164]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Cell::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8231:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Cell::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8231:87: note: '' declared here 8231 | string tmp_158 = boost::python::extract(data[cntr_157]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Cell::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8231:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Cell::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8231:87: note: '' declared here 8231 | string tmp_158 = boost::python::extract(data[cntr_157]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Cell::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8219:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Cell::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8219:87: note: '' declared here 8219 | string tmp_156 = boost::python::extract(data[cntr_155]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Cell::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:8219:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Cell::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:8219:87: note: '' declared here 8219 | string tmp_156 = boost::python::extract(data[cntr_155]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Process::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6947:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Process::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6947:87: note: '' declared here 6947 | string tmp_118 = boost::python::extract(data[cntr_117]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Process::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6947:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Process::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6947:87: note: '' declared here 6947 | string tmp_118 = boost::python::extract(data[cntr_117]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Process::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6935:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Process::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6935:87: note: '' declared here 6935 | string tmp_116 = boost::python::extract(data[cntr_115]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Process::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6935:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Process::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6935:87: note: '' declared here 6935 | string tmp_116 = boost::python::extract(data[cntr_115]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::SwitchRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6695:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::SwitchRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6695:87: note: '' declared here 6695 | string tmp_104 = boost::python::extract(data[cntr_103]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::SwitchRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6695:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::SwitchRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6695:87: note: '' declared here 6695 | string tmp_104 = boost::python::extract(data[cntr_103]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::SwitchRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6683:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::SwitchRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6683:87: note: '' declared here 6683 | string tmp_102 = boost::python::extract(data[cntr_101]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::SwitchRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6683:66: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::SwitchRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6683:87: note: '' declared here 6683 | string tmp_102 = boost::python::extract(data[cntr_101]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::CaseRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6515:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::CaseRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6515:85: note: '' declared here 6515 | string tmp_93 = boost::python::extract(data[cntr_92]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::CaseRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6515:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::CaseRule::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6515:85: note: '' declared here 6515 | string tmp_93 = boost::python::extract(data[cntr_92]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::CaseRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6503:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::CaseRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6503:85: note: '' declared here 6503 | string tmp_91 = boost::python::extract(data[cntr_90]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::CaseRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6503:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::CaseRule::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6503:85: note: '' declared here 6503 | string tmp_91 = boost::python::extract(data[cntr_90]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::NamedObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6048:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::NamedObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6048:85: note: '' declared here 6048 | string tmp_66 = boost::python::extract(data[cntr_65]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::NamedObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6048:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::NamedObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6048:85: note: '' declared here 6048 | string tmp_66 = boost::python::extract(data[cntr_65]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::NamedObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6036:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::NamedObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6036:85: note: '' declared here 6036 | string tmp_64 = boost::python::extract(data[cntr_63]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::NamedObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:6036:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::NamedObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:6036:85: note: '' declared here 6036 | string tmp_64 = boost::python::extract(data[cntr_63]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::AttrObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:5904:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::AttrObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:5904:85: note: '' declared here 5904 | string tmp_58 = boost::python::extract(data[cntr_57]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::AttrObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:5904:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::AttrObject::add_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:5904:85: note: '' declared here 5904 | string tmp_58 = boost::python::extract(data[cntr_57]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::AttrObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:5892:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::AttrObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:5892:85: note: '' declared here 5892 | string tmp_56 = boost::python::extract(data[cntr_55]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::AttrObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)' at kernel/python_wrappers.cc:5892:64: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::AttrObject::set_strpool_attribute(const YOSYS_PYTHON::IdString*, boost::python::list)': kernel/python_wrappers.cc:5892:85: note: '' declared here 5892 | string tmp_56 = boost::python::extract(data[cntr_55]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Design::set_var_py_scratchpad(boost::python::dict)' at kernel/python_wrappers.cc:12654:84: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Design::set_var_py_scratchpad(boost::python::dict)': kernel/python_wrappers.cc:12654:105: note: '' declared here 12654 | string val_tmp_231 = boost::python::extract(rhs[rhs_keylist[ cntr_230 ]]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::Design::set_var_py_scratchpad(boost::python::dict)' at kernel/python_wrappers.cc:12653:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In member function 'void YOSYS_PYTHON::Design::set_var_py_scratchpad(boost::python::dict)': kernel/python_wrappers.cc:12653:100: note: '' declared here 12653 | string key_tmp_231 = boost::python::extract(rhs_keylist[ cntr_230 ]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_constpad(boost::python::dict)' at kernel/python_wrappers.cc:14318:84: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_constpad(boost::python::dict)': kernel/python_wrappers.cc:14318:105: note: '' declared here 14318 | string val_tmp_281 = boost::python::extract(rhs[rhs_keylist[ cntr_280 ]]); | ^ In member function 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::size_type std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::length() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:1176:20, inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(const std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:617:20, inlined from 'void YOSYS_PYTHON::set_var_py_constpad(boost::python::dict)' at kernel/python_wrappers.cc:14317:79: /usr/include/c++/15.2.0/bits/basic_string.h:1165:19: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(boost::python::extract, std::allocator > >,boost::python::extract, std::allocator > >::.boost::python::converter::extract_rvalue, std::allocator > >::m_data.boost::python::converter::rvalue_from_python_data, std::allocator > >::.boost::python::converter::rvalue_from_python_storage, std::allocator > >::storage)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 1165 | size_type __sz = _M_string_length; | ^~~~ kernel/python_wrappers.cc: In function 'void YOSYS_PYTHON::set_var_py_constpad(boost::python::dict)': kernel/python_wrappers.cc:14317:100: note: '' declared here 14317 | string key_tmp_281 = boost::python::extract(rhs_keylist[ cntr_280 ]); | ^ [100%] Building yosys [100%] Building libyosys.so Build successful. [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] ENABLE_ABC:=1 cd tests/arch/anlogic/ && bash run-test.sh cd tests/arch/ecp5/ && bash run-test.sh cd tests/arch/efinix/ && bash run-test.sh cd tests/arch/gatemate/ && bash run-test.sh cd tests/arch/gowin/ && bash run-test.sh cd tests/arch/ice40/ && bash run-test.sh cd tests/arch/intel_alm/ && bash run-test.sh cd tests/arch/machxo2/ && bash run-test.sh cd tests/arch/microchip/ && bash run-test.sh cd tests/arch/nanoxplore/ && bash run-test.sh cd tests/arch/nexus/ && bash run-test.sh cd tests/arch/quicklogic/pp3/ && bash run-test.sh cd tests/arch/quicklogic/qlf_k6n10f/ && bash run-test.sh cd tests/arch/xilinx/ && bash run-test.sh cd tests/bugpoint/ && bash run-test.sh cd tests/opt/ && bash run-test.sh cd tests/sat/ && bash run-test.sh cd tests/sim/ && bash run-test.sh cd tests/svtypes/ && bash run-test.sh cd tests/techmap/ && bash run-test.sh cd tests/various/ && bash run-test.sh cd tests/verilog/ && bash run-test.sh Generate FST for sim models cd tests/memories && bash run-test.sh "-A abc" "" Test tb_adff cd tests/aiger && bash run-test.sh "-A abc" "" cd tests/alumacc && bash run-test.sh "-A abc" "" Checking and_.aag. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memories' cd tests/simple && bash run-test.sh "" Running basic.ys.. cd tests/simple_abc9 && bash run-test.sh "" + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c cd tests/hana && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/simple' + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c ls: *.sv: No such file or directory + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c cd tests/asicworld && bash run-test.sh "" + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c cd tests/share && bash run-test.sh "" + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/hana' -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.cFST info: dumpfile tb_adff.fst opened for output. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/asicworld' + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o + /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata cc /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c-Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c tb/tb_adff.v:38: $finish called at 110 (1ns) + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c generating tests.. + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c Test tb_adffe + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/simple_abc9' + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c FST info: dumpfile tb_adffe.fst opened for output. tb/tb_adffe.v:56: $finish called at 190 (1ns) Test tb_adlatch + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c FST info: dumpfile tb_adlatch.fst opened for output. tb/tb_adlatch.v:68: $finish called at 250 (1ns) Test tb_aldff + cc -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c FST info: dumpfile tb_aldff.fst opened for output. tb/tb_aldff.v:71: $finish called at 270 (1ns) Test tb_aldffe FST info: dumpfile tb_aldffe.fst opened for output. tb/tb_aldffe.v:73: $finish called at 270 (1ns) Test tb_dff running tests.. FST info: dumpfile tb_dff.fst opened for output. [0]tb/tb_dff.v:45: $finish called at 150 (1ns) Test tb_dffe FST info: dumpfile tb_dffe.fst opened for output. tb/tb_dffe.v:40: $finish called at 120 (1ns) Test tb_dffsr FST info: dumpfile tb_dffsr.fst opened for output. tb/tb_dffsr.v:67: $finish called at 250 (1ns) Test tb_dlatch Checking and_to_bad_out.aag. FST info: dumpfile tb_dlatch.fst opened for output. tb/tb_dlatch.v:48: $finish called at 160 (1ns) [1]Test tb_dlatchsr FST info: dumpfile tb_dlatchsr.fst opened for output. tb/tb_dlatchsr.v:63: $finish called at 250 (1ns) Test tb_sdff FST info: dumpfile tb_sdff.fst opened for output. tb/tb_sdff.v:46: $finish called at 150 (1ns) Test tb_sdffce FST info: dumpfile tb_sdffce.fst opened for output. tb/tb_sdffce.v:77: $finish called at 300 (1ns) Test tb_sdffe [2]FST info: dumpfile tb_sdffe.fst opened for output. tb/tb_sdffe.v:68: $finish called at 250 (1ns) [3]Checking buffer.aag. [4]Running macc_b_port_compat.ys.. [5]Test: case_expr_extend -> ok Test: matching_end_labels -> ok Test: local_loop_var -> ok Test: case_expr_query -> ok cd tests/opt_share && bash run-test.sh "" Checking cnt1.aag. [6]generating tests.. Running macc_infer_n_unmap.ys.. Test: memwr_port_connection -> ok [7]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. ...passed tests in tests/alumacc Test: aes_kexp128 -> ok [8]Checking cnt1e.aag. running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/opt_share' [0][9]Test: test_simulation_buffer -> ok [1]Test: lesser_size_cast -> ok Test: code_hdl_models_GrayCounter -> ok cd tests/fsm && bash run-test.sh "" generating tests.. [10][11]Checking empty.aag. PRNG seed: 3532207206677127835 Test: code_hdl_models_arbiter -> ok Test: always01 -> ok [12]Test: implicit_ports -> ok [2]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Warning: The current network has no primary outputs. Some commands may not work correctly. Test: arrays02 -> ok cd tests/memlib && bash run-test.sh "" running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/fsm' [0][13]Test: code_hdl_models_clk_div -> ok [1]Checking false.aag. [14]Test: always02 -> ok [15]make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memlib' Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Test: always03 -> ok Test: firrtl_938 -> ok [3][16]Checking halfadder.aag. Test: implicit_en -> ok [17]Test: no_implicit_en -> ok Test: macro_arg_spaces -> ok cd tests/bram && bash run-test.sh "" generating tests.. Test: code_hdl_models_d_ff_gates -> ok [18]Test: defvalue -> ok Test: test_parse2synthtrans -> ok [2]Test: unnamed_block_decl -> ok [4][19]Test: simple_sram_byte_en -> ok Checking inverter.aag. [5]Test: code_hdl_models_d_latch_gates -> ok [6][20]cd tests/svinterfaces && bash run-test.sh "" Test: svinterface1 -> Test: arrays01 -> ok [21]PRNG seed: 663147 Checking notcnt1.aag. [22]running tests.. Test: arraycells -> ok make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bram' Test: wide_thru_priority -> ok Test: code_hdl_models_clk_div_45 -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [23]Test: shared_ports -> ok [3]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Test: attrib01_module -> ok [24]Test: t_async_small -> ok [4]Checking notcnt1e.aag. Test: test_simulation_and -> ok [7]Test: t_async_small_block -> ok [8][25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [9]Test: code_hdl_models_decoder_2to4_gates -> ok cd tests/xprop && bash run-test.sh "" KChecking or_.aag. Test: wide_read_async -> ok [5]Test: wide_all -> ok [6]Test: test_parser -> ok [7]xprop PRNG seed: 2037680748 make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/xprop' Test: t_sync_big -> ok [8]Test: wide_write -> ok [9]Test: wide_read_sync -> ok Test: read_arst -> ok Test: t_sync_big_sdp -> ok Test: attrib02_port_decl -> ok Test: trans_addr_enable -> ok [10][10]Test: read_two_mux -> ok [11][26]Checking symbols.aag. KTest: aes_kexp128 -> ok Test: wide_read_trans -> ok cd tests/select && bash run-test.sh "" Running boxes_equals_name.ys.. Test: trans_sp -> ok Test: trans_sdp -> ok Running boxes_equals_operators.ys.. [27]Test: wide_read_mixed -> ok Test: test_simulation_inc -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Running boxes_equals_pattern.ys.. [28]Running boxes_equals_wildcard.ys.. Checking toggle-re.aag. Running boxes_import.ys.. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [29]Test: always01 -> ok [11]Test: issue00710 -> ok Warning: Selection "wb" did not match any module. ERROR: No top module found in source design. Expected error pattern 'No top module found in source design\.' found !!! Running boxes_no_equals.ys.. Test: attrib03_parameter -> ok [30]Running boxes_no_equals_clean.ys.. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Selection "wb" did not match any module. Running boxes_setattr.ys.. [31]Checking toggle.aag. Running boxes_stack.ys.. [32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Running internal_selects.ys.. Passed memory_bram test 00_01. Warning: Ignoring blackbox module bb. Warning: Ignoring boxed module wb. Warning: Ignoring boxed module bb. Warning: Ignoring partially selected module wb. Warning: Ignoring partially selected module top. Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Running list_mod.ys.. Test: amber23_sram_byte_en -> ok cd tests/peepopt && bash run-test.sh "" Running muldiv_c.ys.. [33]Running mod-attribute.ys.. Test: arrays03 -> ok Test: attrib04_net_var -> ok Checking true.aag. [34]Test: test_simulation_nand -> ok Test: t_sync_small -> ok Running no_warn_assert.ys.. Test: test_simulation_decoder -> ok Running no_warn_prefixed_arg_memb.ys.. Test: test_simulation_nor -> ok [12][35]KWarning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Passed memory_bram test 00_03. [12]svinterface1_tb.v:50: $finish called at 420000 (10ps) Running no_warn_prefixed_empty_select_arg.ys.. Test: always02 -> ok [36]svinterface1_tb.v:50: $finish called at 420000 (10ps) ok Test: svinterface_at_top -> Running unset.ys.. Checking and_.aig. cd tests/proc && bash run-test.sh "" Running bug2619.ys.. ERROR: Selection '\foo' does not exist! Expected error pattern 'Selection '\\foo' does not exist!' found !!! Running unset2.ys.. [37]Running bug2656.ys.. KERROR: Selection @foo is not defined! Expected error pattern 'Selection @foo is not defined!' found !!! Test: attrib06_operator_suffix -> ok Running warn_empty_select_arg.ys.. Warning: wire '\q1' is assigned in a block at < ok Test: code_hdl_models_decoder_using_assign -> ok [13]Running bug4712.ys.. Passed memory_bram test 00_04. Checking and_to_bad_out.aig. Warning: Async reset value `\a_r' is not constant! [39]Running bug_1268.ys.. Test: test_simulation_always -> ok Running case_attr.ys.. Kcd tests/blif && bash run-test.sh "" Running bug2729.ys.. [40]Test: t_sync_small_block -> ok Running bug3374.ys.. Passed memory_bram test 01_00. Test: test_simulation_seq -> ok Running clean_undef_case.ys.. [41]ERROR: Syntax error in line 1! Expected error pattern 'Syntax error in line 1!' found !!! Passed memory_bram test 01_03. Running bug3385.ys.. Checking buffer.aig. Running proc_dff.ys.. xprop_not_3s_5: ok ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals. Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!! xprop_not_3s_5: ok cd tests/arch && bash run-test.sh "" Running syntax check on arch sim models Test ../../techlibs/achronix/speedster22i/cells_sim.v ->...passed tests in tests/blif ok Test ../../techlibs/anlogic/cells_sim.v ->[42] ok Test ../../techlibs/coolrunner2/cells_sim.v ->Warning: Complex async reset for dff `\q'. ok Test ../../techlibs/ecp5/cells_sim.v -> ok Test ../../techlibs/efinix/cells_sim.v ->Running proc_rom.ys.. ok Test ../../techlibs/gatemate/cells_sim.v ->xprop_pos_3s_5: ok [43]xprop_pos_3s_5: ok Warning: wire '\d' is assigned in a block at <[44]Checking cnt1.aig. Warning: wire '\d' is assigned in a block at <Test: attrib09_case -> ok Kcd tests/rpc && bash run-test.sh "" ok Running exec.ys.. Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->Warning: wire '\d' is assigned in a block at <[45]Test: test_simulation_or -> ok Test: code_hdl_models_decoder_using_case -> ok ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Warning: wire '\d' is assigned in a block at <../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. [46]Running rmdead.ys.. Test: case_expr_const -> ok ok Test ../../techlibs/intel/max10/cells_sim.v ->Test: carryadd -> ok ok Test ../../techlibs/intel/cycloneive/cells_sim.v ->Checking cnt1e.aig. ok Test ../../techlibs/intel/cycloneiv/cells_sim.v ->Test: code_hdl_models_dff_async_reset -> ok ok Test ../../techlibs/intel/cyclone10lp/cells_sim.v ->[47]...passed tests in tests/proc [14] ok Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok Test ../../techlibs/microchip/cells_sim.v ->Test: case_expr_non_const -> ok ok Test ../../techlibs/nanoxplore/cells_sim.v ->[48] ok Test ../../techlibs/nexus/cells_sim.v ->...passed tests in tests/rpc Passed memory_bram test 02_00. [49] ok Test ../../techlibs/quicklogic/common/cells_sim.v -> ok Test ../../techlibs/quicklogic/pp3/cells_sim.v ->Checking empty.aig. ok Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v ->Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! ok Test ../../techlibs/sf2/cells_sim.v -> ok Test ../../techlibs/xilinx/cells_sim.v ->[50]KWarning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Warning: The current network has no primary outputs. Some commands may not work correctly. Passed memory_bram test 00_02. [13] ok Test ../../techlibs/common/simcells.v ->[51]Checking false.aig. ok Test ../../techlibs/common/simlib.v ->Test: code_hdl_models_dff_sync_reset -> ok Test: code_hdl_models_encoder_4to2_gates -> ok cd tests/memfile && bash run-test.sh "" Running from the parent directory with content1.dat ok Test: t_sync_small_block_attr -> ok [52]...passed tests in tests/arch Running from the parent directory with temp/content2.dat Test: test_simulation_mux -> ok [15]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. [53]KRunning from the parent directory with memfile/temp/content2.dat Test: t_init_lut_zeros_zero -> ok [54]Running from the same directory with content1.dat Test: arrays01 -> ok Checking halfadder.aig. Test: t_init_lut_zeros_any -> ok Running from the same directory with temp/content2.dat [55]Kcd tests/fmt && bash run-test.sh "" + awk '/<<>>/,/<<>>/ {print $0}' + ../../yosys -p 'read_verilog initial_display.v' Running from a child directory with content1.dat Test: t_init_lut_val_zero -> ok xprop_and_1u1_1: ok xprop_and_1u1_1: ok svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) Test: arraycells -> ok Running from a child directory with temp/content2.dat svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) [56]ERROR! Test: load_and_derive ->Passed memory_bram test 01_02. + iverilog -o iverilog-initial_display initial_display.v + ./iverilog-initial_display Running from a child directory with content2.dat + diff yosys-initial_display.log iverilog-initial_display.log + test_always_display clk -DEVENT_CLK + local subtest=clk + shift + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v ok Test: resolve_types ->[57]KTest: t_init_lut_val_any -> ok Kxprop_neg_3s_5: ok xprop_neg_3s_5: ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:4$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:4$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Checking inverter.aig. Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 4. Executing Verilog backend. Checking a failure when zero length filename is provided 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 0de35d2746, CPU: user 0.03s system 0.02s, MEM: 27.97 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 40% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... ok + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v ...passed tests in tests/svinterfaces memory.v:15: ERROR: Can not open file `` for \$readmemb. Execution failed, which is OK. Checking a failure when not existing filename is provided [58]Test: always03 -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Execution failed, which is OK. Dumping module `\m'. End of script. Logfile hash: e35e8bb689, CPU: user 0.04s system 0.01s, MEM: 27.44 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 40% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... ...passed tests in tests/memfile [16]+ diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v + test_always_display clk_rst -DEVENT_CLK_RST + local subtest=clk_rst + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v Test: attrib01_module -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:7$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). [59] 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:7$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. [14]Dumping module `\m'. End of script. Logfile hash: c95608ddf0, CPU: user 0.03s system 0.01s, MEM: 27.71 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 41% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: faf50513c3, CPU: user 0.03s system 0.01s, MEM: 28.21 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 39% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v Checking notcnt1.aig. + test_always_display star -DEVENT_STAR + local subtest=star + shift + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v [60] [15] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:10$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:10$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7b2c5274a5, CPU: user 0.03s system 0.01s, MEM: 28.66 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 40% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... Test: attrib02_port_decl -> ok [16]+ ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v [61] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Passed memory_bram test 02_03. Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. [17]Dumping module `\m'. End of script. Logfile hash: 8979c5de0b, CPU: user 0.04s system 0.00s, MEM: 28.31 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 41% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... Test: t_init_lut_val_no_undef -> ok + diff yosys-always_display-star-1.v yosys-always_display-star-2.v + test_always_display clk_en -DEVENT_CLK -DCOND_EN + local subtest=clk_en + shift + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Passed memory_bram test 02_01. K[17] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:4$1'. 1/1: $display$0x7fb8ed16bdc0:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. Removing empty process `m.$proc$always_display.v:4$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 9f985fdd1a, CPU: user 0.03s system 0.01s, MEM: 27.80 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 45% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... [62]+ ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v cd tests/cxxrtl && bash run-test.sh "" + run_subtest value + local subtest=value + shift + cc -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++ /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1/1: $write$0x7fa13792adc0:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. Checking notcnt1e.aig. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7a05e97c22, CPU: user 0.03s system 0.01s, MEM: 28.22 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 42% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... Test: t_async_big -> ok [18][18]+ diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN + local subtest=clk_rst_en + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v [63]Test: code_hdl_models_full_adder_gates -> ok xprop_and_1s1_2: ok xprop_and_1s1_2: ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:7$1'. 1/1: $display$0x7f6d5b5d3dc0:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. Removing empty process `m.$proc$always_display.v:7$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: c876207e62, CPU: user 0.03s system 0.01s, MEM: 28.17 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 38% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v Test: t_init_lut_val2_any -> ok [19][64]Test: test_simulation_vlib -> ok [20] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1/1: $write$0x7f89a7a33dc0:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Passed memory_bram test 02_04. Dumping module `\m'. End of script. Logfile hash: 9ec7fb7bc4, CPU: user 0.04s system 0.01s, MEM: 27.77 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 43% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... Test: test_simulation_sop -> ok cd tests/liberty && bash run-test.sh "" Testing on XNOR2X1.lib.. + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v + test_always_display star_en -DEVENT_STAR -DCOND_EN + local subtest=star_en + shift + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:10$1'. 1/1: $display$0x7ff692472dc0:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. Removing empty process `m.$proc$always_display.v:10$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). [65]Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: bb54c38d21, CPU: user 0.03s system 0.01s, MEM: 28.66 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 45% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... K+ ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v [21] Checking or_.aig. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1/1: $write$0x7f9fc448adc0:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 67e6e5064e, CPU: user 0.04s system 0.01s, MEM: 28.28 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 43% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= + local subtest=dec_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v [66] Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [22] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: bfb187b86d, CPU: user 0.03s system 0.01s, MEM: 27.83 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... Test: code_hdl_models_half_adder_gates -> ok + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v Test: code_hdl_models_full_subtracter_gates -> ok Test: code_hdl_models_encoder_using_case -> ok Passed memory_bram test 01_04. make -C tests/arch/anlogic -f run-test.mk /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/anlogic' 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 4be9539e85, CPU: user 0.03s system 0.01s, MEM: 27.99 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v Test: const_branch_finish -> ok [67]+ ./iverilog-roundtrip-dec_unsigned [23]+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned-1 Test: code_hdl_models_encoder_using_if -> ok [24]+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned-1 Checking symbols.aig. + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log [68]+ diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed + local subtest=dec_signed + shift + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v Testing on busdef.lib.. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. [19]Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. [25]Dumping module `\m'. End of script. Logfile hash: bbdfa5ca92, CPU: user 0.03s system 0.01s, MEM: 28.16 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v Test: code_hdl_models_lfsr -> ok [26] [69] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Test: code_hdl_models_gray_counter -> ok Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: b233de92a6, CPU: user 0.03s system 0.01s, MEM: 27.95 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v [70]+ ./iverilog-roundtrip-dec_signed-1 + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed-1 [27]Checking toggle-re.aig. + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= + local subtest=hex_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v Test: attrib06_operator_suffix -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 2377f2e106, CPU: user 0.03s system 0.01s, MEM: 28.62 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... [71]Passed memory_bram test 03_01. + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v [20][28] Test: attrib04_net_var -> ok Test: attrib03_parameter -> ok Test: code_hdl_models_mux_2to1_gates -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 06bfea69c8, CPU: user 0.03s system 0.01s, MEM: 28.50 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v Test: code_hdl_models_lfsr_updown -> ok make -C tests/arch/ecp5 -f run-test.mk + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v [72]make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ecp5' Testing on dff.lib.. + ./iverilog-roundtrip-hex_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed + local subtest=hex_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v [29][73] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). Test: test_simulation_techmap -> ok 2.9. Executing PROC_DFF pass (convert process syncs to FFs). Test: const_fold_func -> ok 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). [30]Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 824c3b1e65, CPU: user 0.03s system 0.01s, MEM: 28.12 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... ...passed tests in tests/peepopt + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v Test: t_init_lut_val2_no_undef -> ok Checking toggle.aig. [74] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: f18b3fa15b, CPU: user 0.03s system 0.01s, MEM: 27.79 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v Test: test_simulation_xnor -> ok [31][32]+ ./iverilog-roundtrip-hex_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed-1 + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= + local subtest=oct_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v [75]Passed memory_bram test 03_00. Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Kmake -C tests/arch/efinix -f run-test.mk [33]make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/efinix' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: b768358a65, CPU: user 0.03s system 0.01s, MEM: 28.11 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... Passed memory_bram test 03_02. [34]+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v [76] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Checking true.aig. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 762621cd95, CPU: user 0.03s system 0.01s, MEM: 27.73 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... Testing on idranges.lib.. + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned-1 + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v Test: issue00335 -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memories' + ./iverilog-roundtrip-oct_unsigned-1 Testing expectations for amber23_sram_byte_en.v ..Test: asgn_binop -> ok Test: t_sync_big_lut -> ok + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log [21]+ diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed + local subtest=oct_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v [77][35] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Warning: The new network has no primary inputs. It is recommended Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). to add a dummy PI to make sure all commands work correctly. 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7ec82b15e3, CPU: user 0.03s system 0.01s, MEM: 28.16 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v [78]Test: test_simulation_xor -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). Test: t_init_lut_x_none -> ok 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). [36]Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: a747b9bd4f, CPU: user 0.03s system 0.01s, MEM: 28.21 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 27% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v Test: attrib08_mod_inst -> ok + ./iverilog-roundtrip-oct_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v Running io.ys. + ./iverilog-roundtrip-oct_signed-1 [79]+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v Warning: reg '\out' is assigned in a continuous assignment at < | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v + ./cxxrtl-test-value Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. + run_subtest value_fuzz + local subtest=value_fuzz + shift + cc -std=c++11 -O2 -o cxxrtl-test-value_fuzz -I../../backends/cxxrtl/runtime test_value_fuzz.cc -lstdc++ Dumping module `\m'. End of script. Logfile hash: 270b564880, CPU: user 0.03s system 0.01s, MEM: 28.32 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v xprop_or_1u1_1: ok xprop_or_1u1_1: ok ...passed tests in tests/aiger Testing on issue3498_bad.lib.. [38] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). Passed efinix-add_sub.ys 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). [39] 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: dc9f56cb10, CPU: user 0.03s system 0.01s, MEM: 28.40 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 27% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned Passed memory_bram test 03_04. [22][81]+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned-1 Test: case_expr_const -> ok + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v Kxprop_or_1s1_2: ok xprop_or_1s1_2: ok + ./iverilog-roundtrip-bin_unsigned-1 + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed + local subtest=bin_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v Test: attrib09_case -> ok Passed efinix-counter.ys [82] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7709253822, CPU: user 0.03s system 0.01s, MEM: 28.16 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... [40]xprop_and_2u2_2: ok xprop_and_2u2_2: ok + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v [41]K[42] Test: code_hdl_models_mux_using_assign -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7e2d8271c4, CPU: user 0.03s system 0.01s, MEM: 28.12 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 24% 1x opt_expr (0 sec), ... ok. Testing expectations for implicit_en.v ..+ diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v [83]+ ./iverilog-roundtrip-bin_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! + ./iverilog-roundtrip-bin_signed-1 [43]+ diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log [84]+ test_cxxrtl always_full + local subtest=always_full + shift + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' Test: carryadd -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1. Executing Verilog-2005 frontend: always_full.v ok. Testing expectations for issue00335.v ..Parsing Verilog input from `always_full.v' to AST representation. Generating RTLIL representation for module `\always_full'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 207 redundant assignments. Promoted 207 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `always_full.$proc$always_full.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. Removed 0 unused cells and 207 unused wires. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. root of 0 design levels: always_full Automatically selected always_full as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \always_full 3.1.3. Analyzing design hierarchy.. Top module: \always_full Removed 0 unused modules. Module always_full directly or indirectly displays text -> setting "keep" attribute. 3.2. Executing FLATTEN pass (flatten design). 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Testing on non-ascii.lib.. Optimizing module always_full. End of script. Logfile hash: af8795c7c4, CPU: user 0.06s system 0.02s, MEM: 29.84 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 39% 2x read_verilog (0 sec), 18% 2x write_cxxrtl (0 sec), ... [85]+ cc -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++ Test: constpower -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed efinix-adffs.ys [86]Passed efinix-dffs.ys [23]Passed anlogic-add_sub.ys [44]Passed memory_bram test 04_00. ok. Testing expectations for issue00710.v ..[87]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! ok. Testing expectations for no_implicit_en.v ..Testing on normal.lib.. Passed anlogic-counter.ys make -C tests/arch/gatemate -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gatemate' Test: abc9 -> ok Test: t_init_lut_x_zero -> ok xprop_or_2u2_2: ok xprop_or_2u2_2: ok [88]K[45] ok. Testing expectations for read_arst.v ..[89]KTest: case_expr_non_const -> ok [90]Passed memory_bram test 04_02. make -C tests/arch/gowin -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gowin' Test: code_hdl_models_mux_using_case -> ok ok. Testing expectations for read_two_mux.v ..[91]Testing on processdefs.lib.. [92]Test: t_init_lut_x_any -> ok ok. Testing expectations for shared_ports.v ..K[93]Passed memory_bram test 04_03. make -C tests/arch/ice40 -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ice40' Passed efinix-fsm.ys [94] ok. Testing expectations for simple_sram_byte_en.v ..Passed ecp5-add_sub.ys Test: fiedler-cooley -> ok [95]Testing on semicolextra.lib.. [96]Passed efinix-logic.ys ok. Testing expectations for trans_addr_enable.v ..Test: t_init_lut_x_no_undef -> ok [97]Test: dff_init -> ok [98] ok. Testing expectations for trans_sdp.v ..[99]Test: code_hdl_models_mux_using_if -> ok [46]Test: const_func_shadow -> ok Test: t_ram_18b2B -> ok Test: forgen01 -> ok ok. Testing expectations for trans_sp.v ..Test: code_hdl_models_one_hot_cnt -> ok < ok make -C tests/arch/intel_alm -f run-test.mk ...passed tests in tests/share Testing on semicolmissing.lib.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/intel_alm' ok. Testing expectations for wide_all.v ..Passed anlogic-logic.ys Passed ecp5-bug1459.ys Passed efinix-latches.ys KPassed efinix-lutram.ys [47]Test: forgen02 -> ok Passed anlogic-fsm.ys ok. Testing expectations for wide_read_async.v ..Passed ecp5-bug1598.ys ok. Testing expectations for wide_read_mixed.v ..Running libcache.ys.. Running options_test.ys.. Passed gowin-add_sub.ys Test: dff_different_styles -> ok ok. Testing expectations for wide_read_sync.v ..xprop_xor_1u1_1: ok xprop_xor_1u1_1: ok Passed ecp5-bug1630.ys ...passed tests in tests/liberty [48]Test: test_simulation_shifter -> ok [24]Passed anlogic-dffs.ys make -C tests/arch/machxo2 -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/machxo2' ok. Testing expectations for wide_read_trans.v ..Test: t_ram_9b1B -> ok Test: t_async_big_block -> ok ok. Testing expectations for wide_thru_priority.v ..Passed efinix-shifter.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: code_hdl_models_parallel_crc -> ok ok. Testing expectations for wide_write.v ..Passed intel_alm-add_sub.ys ok. ...passed tests in tests/memories Passed anlogic-lutram.ys Test: const_fold_func -> ok xprop_xor_1s1_2: ok xprop_xor_1s1_2: ok [49]Test: t_ram_4b1B -> ok [50]Test: forloops -> ok Test: test_intermout -> ok [25][26]Passed gowin-compare.ys Passed gowin-counter.ys xprop_xor_2u2_2: ok xprop_xor_2u2_2: ok Test: t_ram_2b1B -> ok Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. Test: fsm -> ok Test: func_block -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_ram_1b1B -> ok Test: t_init_9b1B_zeros_zero -> ok Passed efinix-tribuf.ys Passed anlogic-shifter.ys Passed machxo2-add_sub.ys Passed anlogic-tribuf.ys make -C tests/arch/microchip -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/microchip' Test: t_init_9b1B_zeros_any -> ok Passed ecp5-bug1836.ys Passed efinix-mux.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/efinix' ...passed tests in tests/arch/efinix K[51]Test: code_hdl_models_parity_using_assign -> ok Test: func_recurse -> ok Passed intel_alm-adffs.ys [27]xprop_xnor_1u1_1: ok xprop_xnor_1u1_1: ok Test: code_hdl_models_parity_using_bitwise -> ok KPassed intel_alm-blockram.ys Test: constmuldivmod -> ok Test: t_init_9b1B_val_zero -> ok Passed machxo2-counter.ys Test: constpower -> ok Passed ice40-add_sub.ys Test: const_func_shadow -> ok [52]Passed anlogic-latches.ys make -C tests/arch/nanoxplore -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nanoxplore' make -C tests/arch/nexus -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nexus' ERROR: FF myDFFP.$auto$ff.cc:266:slice$671 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination Expected error pattern 'unsupported initial value and async reset value combination' found !!! Passed gowin-init-error.ys make -C tests/arch/quicklogic/pp3 -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/pp3' Test: test_simulation_techmap_tech -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/hana' Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. ...passed tests in tests/hana Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_init_9b1B_val_any -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed intel_alm-counter.ys Warning: Complex async reset for dff `\Q'. Passed gatemate-add_sub.ys + ./cxxrtl-test-value_fuzz Randomized tests for value::shl: Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed pp3-add_sub.ys [53]Test: t_init_9b1B_val_no_undef -> ok Warning: Complex async reset for dff `\Q'. Passed gatemate-counter.ys xprop_xnor_1s1_2: ok xprop_xnor_1s1_2: ok Passed gowin-fsm.ys Passed pp3-counter.ys Passed gowin-dffs.ys Test: t_init_13b2B_val_any -> ok Test: dff_init -> ok Passed gowin-adffs.ys Passed intel_alm-dffs.ys [54]Warning: Ignoring boxed module dffepc. Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop. KPassed ecp5-bug2409.ys Test: t_init_18b2B_val_any -> ok Passed ecp5-adffs.ys Passed gatemate-fsm.ys Passed ice40-bug1626.ys make -C tests/arch/quicklogic/qlf_k6n10f -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/qlf_k6n10f' Test: constmuldivmod -> ok Passed ice40-bug1597.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed gatemate-logic.ys Passed machxo2-adffs.ys Test: code_hdl_models_cam -> ok Test: func_width_scope -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed memory_bram test 04_01. make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bram' ...passed tests in tests/bram Passed pp3-adffs.ys [55]Test: t_init_18b2B_val_no_undef -> ok [56]Passed intel_alm-fsm.ys xprop_xnor_2u2_2: ok xprop_xnor_2u2_2: ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Complex async reset for dff `\Q'. Warning: Ignoring boxed module dffepc. [57]Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop. Test: dff_different_styles -> ok Test: t_init_4b1B_x_none -> ok [58]Test: genblk_collide -> ok [59]Passed ice40-bug1598.ys [60]K[61][62]Passed intel_alm-logic.ys [63]Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. [64]Test: t_init_4b1B_x_zero -> ok [65]Test: code_hdl_models_parity_using_function -> ok Passed machxo2-dffs.ys [66]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed anlogic-blockram.ys [67]Passed pp3-dffs.ys Test: t_init_4b1B_x_any -> ok Passed ecp5-bug2731.ys [68]K[69]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. [70][71]Test: dynslice -> ok [72]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: t_init_4b1B_x_no_undef -> ok [73][74]Passed anlogic-mux.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/anlogic' ...passed tests in tests/arch/anlogic + ./yosys-always_full + iverilog -o iverilog-always_full always_full.v always_full_tb.v + grep -v '\$finish called' + ./iverilog-always_full [75]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. + diff iverilog-always_full.log yosys-always_full.log + test_cxxrtl always_comb + local subtest=always_comb + shift + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1. Executing Verilog-2005 frontend: always_comb.v Parsing Verilog input from `always_comb.v' to AST representation. Generating RTLIL representation for module `\top'. Generating RTLIL representation for module `\sub'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$always_comb.v:3$13'. Set init value: \b = 1'0 Found init rule in `\top.$proc$always_comb.v:2$12'. Set init value: \a = 1'0 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1/1: $display$0x7fad88ebedc0:23$19_EN Creating decoders for process `\top.$proc$always_comb.v:3$13'. Creating decoders for process `\top.$proc$always_comb.v:2$12'. Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. created $dff cell `$procdff$22' with positive edge clock. Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. created $dff cell `$procdff$23' with positive edge clock. 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. Removing empty process `sub.$proc$always_comb.v:23$15'. Removing empty process `top.$proc$always_comb.v:3$13'. Removing empty process `top.$proc$always_comb.v:2$12'. Removing empty process `top.$proc$always_comb.v:8$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module sub. Optimizing module top. [76]Removed 0 unused cells and 7 unused wires. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. root of 0 design levels: sub root of 1 design levels: top Automatically selected top as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \top Used module: \sub 3.1.3. Analyzing design hierarchy.. Top module: \top Used module: \sub Removed 0 unused modules. Module sub directly or indirectly displays text -> setting "keep" attribute. Module top directly or indirectly displays text -> setting "keep" attribute. 3.2. Executing FLATTEN pass (flatten design). Deleting now unused module sub. 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. End of script. Logfile hash: bce21a0625, CPU: user 0.04s system 0.01s, MEM: 28.69 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 32% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + cc -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++ Passed machxo2-fsm.ys xprop_add_5u3_3: ok xprop_add_5u3_3: ok [77]Test: t_clock_a4_wANYrANYsFalse -> ok Test: code_hdl_models_pri_encoder_using_assign -> ok [78]Passed pp3-latches.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. KWarning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed ice40-bug2061.ys Test: t_clock_a4_wANYrNEGsFalse -> ok Passed pp3-logic.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_hdl_models_rom_using_case -> ok Passed gatemate-dffs.ys Passed ecp5-counter.ys Passed machxo2-logic.ys Passed qlf_k6n10f-add_sub.ys Test: t_clock_a4_wANYrPOSsFalse -> ok [79][80]Passed gowin-logic.ys Passed ice40-counter.ys [81]Warning: Wire adff.q has an unprocessed 'init' attribute. Warning: Complex async reset for dff `\Q'. xprop_add_5s3_3: ok xprop_add_5s3_3: ok Test: t_clock_a4_wNEGrANYsFalse -> ok Test: t_clock_a4_wNEGrPOSsFalse -> ok [82][83][84]Test: code_hdl_models_serial_crc -> ok Test: genblk_dive -> ok [85][28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_clock_a4_wNEGrNEGsFalse -> ok Passed pp3-mux.ys + ./yosys-always_comb + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v + ./iverilog-always_comb + grep -v '\$finish called' + diff iverilog-always_comb.log yosys-always_comb.log + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v K Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog always_full.v; prep; clean' -- 1. Executing Verilog-2005 frontend: always_full.v Parsing Verilog input from `always_full.v' to AST representation. Generating RTLIL representation for module `\always_full'. Successfully finished Verilog frontend. 2. Executing PREP pass. 2.1. Executing HIERARCHY pass (managing design hierarchy). Module always_full directly or indirectly displays text -> setting "keep" attribute. 2.2. Executing PROC pass (convert processes to netlists). 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 207 redundant assignments. Promoted 207 assignments to connections. 2.2.4. Executing PROC_INIT pass (extract init attributes). 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `always_full.$proc$always_full.v:3$1'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.3. Executing FUTURE pass. 2.4. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. Removed 0 unused cells and 207 unused wires. 2.6. Executing CHECK pass (checking for obvious problems). Checking module always_full... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Removed a total of 0 cells. 2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \always_full.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \always_full. Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.7.7. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.7.8. Finished OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.11.4. Finished fast OPT passes. 2.12. Printing statistics. === always_full === +----------Local Count, excluding submodules. | 1 wires 1 wire bits 1 public wires 1 public wire bits 1 ports 1 port bits 207 cells 207 $print 2.13. Executing CHECK pass (checking for obvious problems). Checking module always_full... Found and reported 0 problems. -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\always_full'. End of script. Logfile hash: 7983665bd1, CPU: user 0.10s system 0.02s, MEM: 29.67 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 21% 2x read_verilog (0 sec), 21% 4x opt_clean (0 sec), ... + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v + ./iverilog-always_full-1 + grep -v '\$finish called' + diff iverilog-always_full.log iverilog-always_full-1.log + ../../yosys -p 'read_verilog display_lm.v' K[29]+ ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' Warning: Complex async reset for dff `\Q'. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1. Executing Verilog-2005 frontend: display_lm.v Parsing Verilog input from `display_lm.v' to AST representation. Generating RTLIL representation for module `\top'. Generating RTLIL representation for module `\mid'. Generating RTLIL representation for module `\bot'. %l: \bot %m: \bot Successfully finished Verilog frontend. 2. Executing CXXRTL backend. 2.1. Executing HIERARCHY pass (managing design hierarchy). 2.1.1. Finding top of design hierarchy.. root of 0 design levels: bot root of 1 design levels: mid root of 2 design levels: top Automatically selected top as design top module. 2.1.2. Analyzing design hierarchy.. Top module: \top Used module: \mid Used module: \bot 2.1.3. Analyzing design hierarchy.. Top module: \top Used module: \mid Used module: \bot Removed 0 unused modules. Module bot directly or indirectly displays text -> setting "keep" attribute. Module mid directly or indirectly displays text -> setting "keep" attribute. Module top directly or indirectly displays text -> setting "keep" attribute. 2.2. Executing FLATTEN pass (flatten design). Deleting now unused module bot. Deleting now unused module mid. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 2 assignments to connections. 2.3.4. Executing PROC_INIT pass (extract init attributes). 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:10$3'. Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:10$3'. Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. Cleaned up 0 empty switches. 2.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. End of script. Logfile hash: ba0468a5ee, CPU: user 0.03s system 0.01s, MEM: 28.23 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 38% 1x opt_expr (0 sec), 17% 2x read_verilog (0 sec), ... + cc -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ Passed qlf_k6n10f-counter.ys Test: t_clock_a4_wPOSrANYsFalse -> ok Passed pp3-tribuf.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/pp3' ...passed tests in tests/arch/quicklogic/pp3 Test: code_hdl_models_tff_async_reset -> ok xprop_sub_5u3_3: ok xprop_sub_5u3_3: ok Test: t_clock_a4_wPOSrNEGsFalse -> ok Passed gowin-init.ys Passed intel_alm-lutram.ys Passed ecp5-dffs.ys Passed microchip-dff_opt.ys Test: case_large -> ok Test: code_hdl_models_tff_sync_reset -> ok Test: t_clock_a4_wPOSrPOSsFalse -> ok Test: t_clock_a4_wANYrANYsTrue -> ok [86][87]+ ./yosys-display_lm_cc + for log in yosys-display_lm.log yosys-display_lm_cc.log + grep '^%l: \\bot$' yosys-display_lm.log %l: \bot + grep '^%m: \\bot$' yosys-display_lm.log %m: \bot + for log in yosys-display_lm.log yosys-display_lm_cc.log + grep '^%l: \\bot$' yosys-display_lm_cc.log %l: \bot %l: \bot + grep '^%m: \\bot$' yosys-display_lm_cc.log %m: \bot %m: \bot ...passed tests in tests/fmt xprop_sub_5s3_3: ok xprop_sub_5s3_3: ok Warning: Wire adffn.q has an unprocessed 'init' attribute. [88][89]Passed gatemate-latches.ys Test: t_clock_a4_wNEGrPOSsTrue -> ok [90]Test: fiedler-cooley -> ok Passed ice40-dffs.ys [91]Passed microchip-reduce.ys [92][93]Passed ice40-adffs.ys [94]K[30][95]Test: t_clock_a4_wNEGrNEGsTrue -> ok [96][97][98]Passed intel_alm-mul.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [99]Test: t_clock_a4_wPOSrNEGsTrue -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/opt_share' ...passed tests in tests/opt_share Warning: Wire my_dffe.q has an unprocessed 'init' attribute. Test: forgen01 -> ok Test: genblk_order -> ok Passed ecp5-dpram.ys Passed qlf_k6n10f-dffs.ys Test: t_clock_a4_wPOSrPOSsTrue -> ok Passed intel_alm-shifter.ys xprop_mul_5u3_3: ok xprop_mul_5u3_3: ok Passed nexus-counter.ys Test: t_unmixed -> ok Test: code_hdl_models_up_counter -> ok Test: forgen02 -> ok Passed gowin-shifter.ys Test: code_hdl_models_uart -> ok Test: t_mixed_9_18 -> ok Passed machxo2-shifter.ys Passed machxo2-mux.ys [31]Passed microchip-uram_ar.ys Test: dynslice -> ok Test: t_mixed_18_9 -> ok Passed gatemate-adffs.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: forloops -> ok Test: t_mixed_36_9 -> ok Passed intel_alm-tribuf.ys Passed intel_alm-mux.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/intel_alm' ...passed tests in tests/arch/intel_alm Passed ecp5-fsm.ys [32]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. KWarning: Wire dffs.q has an unprocessed 'init' attribute. xprop_mul_5s3_3: ok xprop_mul_5s3_3: ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_hdl_models_up_counter_load -> ok Test: t_mixed_4_2 -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed gowin-tribuf.ys Passed gatemate-shifter.ys Test: t_tdp -> ok Test: genblk_port_shadow -> ok Passed gowin-mux.ys xprop_div_5u3_3: ok xprop_div_5u3_3: ok Test: t_sync_2clk -> ok Test: fsm -> ok Test: code_hdl_models_up_down_counter -> ok Test: code_specman_switch_fabric -> ok Passed microchip-uram_sr.ys Passed microchip-simple_ram.ys Passed nexus-fsm.ys [33]Passed machxo2-tribuf.ys Test: t_sync_shared -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! xprop_div_5s3_3: ok xprop_div_5s3_3: ok Test: func_block -> ok Passed ecp5-latches_abc9.ys Passed gatemate-mul.ys Test: code_tidbits_asyn_reset -> ok Test: t_sync_2clk_shared -> ok Test: genblk_collide -> ok KPassed gatemate-tribuf.ys Test: func_recurse -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: t_sync_trans_old_old -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed ice40-ice40_dsp.ys Test: code_tidbits_blocking -> ok Passed ecp5-logic.ys Passed ecp5-latches.ys Warning: Wire ndffnr.q has an unprocessed 'init' attribute. Test: t_sync_trans_old_new -> ok Passed qlf_k6n10f-fsm.ys KPassed qlf_k6n10f-adffs.ys Test: func_width_scope -> ok xprop_mod_5u3_3: ok xprop_mod_5u3_3: ok Test: graphtest -> ok Test: t_sync_trans_old_none -> ok Test: code_tidbits_fsm_using_always -> ok [34]Test: genblk_dive -> ok Passed qlf_k6n10f-div.ys [35]Passed machxo2-lutram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/machxo2' ...passed tests in tests/arch/machxo2 Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sync_trans_new_old -> ok Passed qlf_k6n10f-dsp.ys Passed ice40-fsm.ys Test: genblk_order -> ok xprop_mod_5s3_3: ok xprop_mod_5s3_3: ok Passed gatemate-mux.ys Test: code_tidbits_fsm_using_function -> ok Test: t_sync_trans_new_new -> ok Test: hierarchy -> ok Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::shr: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sshr: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::add: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sub: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::ctlz: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::udivmod (div): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42KTest: genblk_port_shadow -> ok Passed nexus-logic.ys Passed nexus-add_sub.ys make -C tests/arch/xilinx -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/xilinx' Test: t_sp_nc_none -> ok Test: t_sync_trans_new_none -> ok Test: graphtest -> ok Passed qlf_k6n10f-logic.ys Test: t_sp_new_none -> ok Test: hierdefparam -> ok Passed ecp5-macc.ys [36]Test: generate -> ok Test: code_tidbits_fsm_using_single_always -> ok make -C tests/bugpoint -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bugpoint' ERROR: Missing -script or -command option. Expected error pattern 'Missing -script or -command option.' found !!! Passed ecp5-mul.ys make -C tests/opt -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/opt' Passed opt-bug1525.ys ERROR: The provided script file or command and Yosys binary do not crash on this design! Expected error pattern 'do not crash on this design' found !!! Passed nexus-dffs.ys Passed opt-bug1758.ys ERROR: The provided script file or command and Yosys binary returned value 3 instead of expected 7 on this design! Expected error pattern 'returned value 3 instead of expected 7' found !!! Passed opt-bug1854.ys xprop_divfloor_5u3_3: ok xprop_divfloor_5u3_3: ok Test: t_sp_old_none -> ok ERROR: The provided grep string is not found in the log file! Expected error pattern 'not found in the log file!' found !!! Passed opt-bug2010.ys [37]Passed opt-bug2221.ys Test: t_sp_nc_nc -> ok ERROR: The provided grep string is not found in stderr log! Expected error pattern 'not found in stderr log!' found !!! Passed opt-bug2311.ys Passed bugpoint-failures.ys Passed opt-bug2318.ys Test: code_tidbits_nonblocking -> ok Passed opt-bug2623.ys Passed opt-bug2765.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed opt-bug2766.ys Test: hierarchy -> ok Test: t_sp_new_nc -> ok Passed opt-bug2824.ys Passed opt-bug2920.ys KPassed gatemate-luttrees.ys Passed opt-bug3047.ys Test: case_large -> ok Passed opt-bug3117.ys Passed opt-bug3848.ys Passed opt-bug3867.ys Test: code_tidbits_reg_combo_example -> ok Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1934_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1952_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1943_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1949_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1925_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1937_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1928_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1946_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1931_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1940_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1955_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap$mul$< ok Passed opt-bug5164.ys Passed ice40-ice40_dsp_const.ys Passed opt-memory_bmux2rom.ys Test: t_sp_nc_new -> ok Passed nexus-blockram.ys Test: t_sp_new_new -> ok Passed opt-memory_dff_trans.ys KPassed gatemate-memory.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gatemate' ...passed tests in tests/arch/gatemate Test: t_sp_old_new -> ok Test: code_tidbits_reg_seq_example -> ok Test: i2c_master_tests -> ok Passed opt-opt_clean_mem.ys Passed opt-opt_clean_init.ys Passed nanoxplore-fsm.ys xprop_divfloor_5s3_3: ok xprop_divfloor_5s3_3: ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: ifdef_1 -> ok Test: t_sp_nc_old -> ok Passed opt-memory_map_offset.ys KPassed opt-opt_dff-simplify.ys Test: code_tidbits_syn_reset -> ok Passed ice40-dpram.ys Passed opt-opt_dff_arst.ys Test: ifdef_2 -> ok make -C tests/sat -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sat' Test: t_sp_new_old -> ok Passed sat-asserts.ys Test: localparam_attr -> ok Passed opt-opt_dff_clk.ys Passed sat-asserts_seq.ys Passed sat-bug2595.ys Warning: Complex async reset for dff `\q [12]'. Warning: Complex async reset for dff `\q [8]'. xprop_modfloor_5u3_3: ok xprop_modfloor_5u3_3: ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. < ok Test: loop_prefix_case -> ok Passed opt-opt_dff_const.ys Test: code_tidbits_wire_example -> ok < ok K[38]Test: loop_var_shadow -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: code_verilog_tutorial_addbit -> ok Passed opt-opt_dff_en.ys Test: t_sp_new_new_only -> ok Test: hierdefparam -> ok Passed microchip-widemux.ys Test: code_verilog_tutorial_always_example -> ok Test: t_sp_old_new_only -> ok xprop_lt_5u3_2: ok xprop_lt_5u3_2: ok Passed opt-opt_dff_mux.ys Test: t_sp_nc_new_only_be -> ok Test: generate -> ok Passed opt-opt_dff_qd.ys Test: loops -> ok Passed sat-counters-repeat.ys Passed ice40-ice40_opt.ys Passed ice40-ice40_wrapcarry.ys [39]Test: code_verilog_tutorial_bus_con -> ok KPassed nexus-shifter.ys Passed microchip-ram_SDP.ys Test: t_sp_new_new_only_be -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed ecp5-lutram.ys Test: macro_arg_surrounding_spaces -> ok Passed microchip-ram_TDP.ys Passed qlf_k6n10f-latches.ys ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top/c_c top/c_b top/c_a top/w_c top/w_b top/w_a Test: code_verilog_tutorial_comment -> ok ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top/c_b top/c_a top/w_c top/w_b top/w_a Test: code_verilog_tutorial_counter -> ok Test: t_sp_old_new_only_be -> ok ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top/c_b top/c_a top/w_c top/w_b top/w_a ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top top/c_b top/c_a top/w_c top/w_b top/w_a xprop_lt_5s3_2: ok xprop_lt_5s3_2: ok make -C tests/sim -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sim' Passed microchip-mult.ys Passed sim-assume_x_first_step.ys Warning: Resizing cell port pre_post_adder.$mul$< ok Passed sim-sim_adff.ys Test: macros -> ok Passed sim-sim_adffe.ys Passed sim-sim_adlatch.ys Warning: Async reset value `\ad' is not constant! Passed sim-sim_aldff.ys Warning: Async reset value `\ad' is not constant! Passed sim-sim_aldffe.ys Test: i2c_master_tests -> ok Passed sim-sim_cycles.ys Passed sim-sim_dff.ys Test: code_verilog_tutorial_d_ff -> ok Passed opt-opt_dff_sr.ys Passed sim-sim_dffe.ys Test: t_sp_new_new_be -> ok Warning: Complex async reset for dff `\q'. Passed sim-sim_dffsr.ys Passed sim-sim_dlatch.ys Passed nexus-lutram.ys Passed sim-sim_dlatchsr.ys Passed sim-sim_sdff.ys ERROR: help me Passed sim-sim_sdffce.ys Passed opt-opt_dff_srst.ys Passed sim-sim_sdffe.ys Passed sim-vcd_var_reference_whitespace.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sim' ...passed tests in tests/sim Test: ifdef_1 -> ok xprop_le_5u3_2: ok xprop_le_5u3_2: ok ERROR: help me Passed sat-counters.ys Passed opt-opt_expr.ys Test: t_sp_old_new_be -> ok ERROR: No 'raise_error' attribute found ERROR: No 'raise_error' attribute found Passed nanoxplore-logic.ys ERROR: help me Passed opt-opt_expr_alu.ys ERROR: help me Test: code_verilog_tutorial_decoder -> ok ERROR: help me Test: ifdef_2 -> ok Passed opt-opt_expr_and.ys Passed opt-opt_expr_cmp.ys Warning: wire '\a' is assigned in a block at < ok Passed opt-opt_expr_constconn.ys Test: t_sp_nc_old_be -> ok Passed opt-opt_expr_consumex.ys Passed sat-clk2fflogic.ys Passed sat-dff.ys Passed bugpoint-proc_constraints.ys make -C tests/svtypes -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/svtypes' Test: loop_prefix_case -> ok Warning: Shift register inference not yet supported for family xc3s. Passed sat-expose_dff.ys Passed svtypes-enum_simple.ys ERROR: No 'raise_error' attribute found Passed opt-opt_expr_more.ys Test: t_sp_new_old_be -> ok Passed bugpoint-raise_error.ys Passed svtypes-logic_rom.ys Passed bugpoint-mod_constraints.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bugpoint' ...passed tests in tests/bugpoint Test: code_verilog_tutorial_decoder_always -> ok < ok Test: mem2reg_bounds_tern -> ok < ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. xprop_le_5s3_2: ok xprop_le_5s3_2: ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed opt-opt_expr_shift.ys Passed ice40-logic.ys Passed opt-opt_expr_shr_int_max.ys Test: t_sp_old_old_be -> ok Passed sat-initval.ys Passed sat-grom.ys Test: macro_arg_surrounding_spaces -> ok Passed svtypes-struct_dynamic_range.ys Passed opt-opt_expr_xnor.ys Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19. Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19. Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19. Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19. Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19. Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19. Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19. Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19. Passed svtypes-typedef_initial_and_assign.ys Test: code_verilog_tutorial_escape_id -> ok [41]Passed nanoxplore-shifter.ys Passed svtypes-typedef_memory.ys Passed opt-opt_expr_xor.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed svtypes-typedef_memory_2.ys Passed svtypes-typedef_struct_global.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! KTest: t_sp_nc_nc_be -> ok Test: t_sp_new_nc_be -> ok Passed svtypes-typedef_struct_port.ys Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15. Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16. Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21. Passed ecp5-mux.ys Passed svtypes-multirange_array.sv Passed ecp5-opt_lut_ins.ys Passed svtypes-static_cast_simple.sv struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef. struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef. struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef. struct_array.sv:45: Warning: Range [3:-4] select out of bounds on signal `\s_s': Setting 4 LSB bits to undef. struct_array.sv:46: Warning: Range select [23:16] out of bounds on signal `\s_s': Setting all 8 result bits to undef. struct_array.sv:47: Warning: Range [19:12] select out of bounds on signal `\s_s': Setting 4 MSB bits to undef. struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef. struct_array.sv:38: Warning: Range [-1:-8] select out of bounds on signal `\s_s': Setting 8 LSB bits to undef. Passed svtypes-struct_array.sv Passed svtypes-struct_simple.sv K[42]Test: loops -> ok Passed svtypes-struct_sizebits.sv Test: mem_arst -> ok Test: t_sp_nc_auto -> ok Passed svtypes-typedef_package.sv Test: t_sp_old_nc_be -> ok Passed svtypes-typedef_param.sv Passed nanoxplore-dffs.ys Test: code_verilog_tutorial_explicit -> ok Passed svtypes-typedef_scopes.sv Passed svtypes-typedef_simple.sv Passed svtypes-typedef_struct.sv Passed svtypes-union_simple.sv make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/svtypes' ...passed tests in tests/svtypes K[43]Warning: Wire top.\cnt [7] is used but has no driver. Warning: Wire top.\cnt [6] is used but has no driver. Warning: Wire top.\cnt [5] is used but has no driver. Warning: Wire top.\cnt [4] is used but has no driver. Warning: Wire top.\cnt [3] is used but has no driver. Warning: Wire top.\cnt [2] is used but has no driver. Warning: Wire top.\cnt [1] is used but has no driver. Warning: Wire top.\cnt [0] is used but has no driver. xprop_eq_5u3_2: ok Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000' ERROR: Signal difference Expected error pattern 'Signal difference' found !!! xprop_eq_5u3_2: ok Passed sat-sim_counter.ys Passed opt-opt_lut_elim.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: t_sp_new_auto -> ok Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. Test: code_verilog_tutorial_first_counter -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed nexus-tribuf.ys Test: t_sp_old_auto -> ok Test: macros -> ok Passed ecp5-rom.ys Passed sat-share.ys Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. Passed sat-sizebits.ys Passed ecp5-shifter.ys Test: code_verilog_tutorial_flip_flop -> ok Passed sat-splice.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sat' ...passed tests in tests/sat Test: t_sp_nc_auto_be -> ok /home/buildozer/aports/testing/yosys/src/share/ice40/cells_sim.v:41: Warning: Yosys has only limited support for tri-state logic at the moment. Test: module_scope_case -> ok Test: t_sp_new_auto_be -> ok /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2663: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_RDATA': Setting 18 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2709: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_RDATA': Setting 18 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Range [4:1] select out of bounds on signal `\PORT_A1_WR_BE': Setting 3 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Ignoring assignment to constant bits: old assignment: { 3'x \PORT_A1_WR_BE [1] } = 4'0000 new assignment: \PORT_A1_WR_BE [1] = 1'0. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Range [3:0] select out of bounds on signal `\PORT_A1_WR_BE': Setting 2 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Ignoring assignment to constant bits: old assignment: { 2'x \PORT_A1_WR_BE } = \PORT_A1_WR_BE_i new assignment: \PORT_A1_WR_BE = \PORT_A1_WR_BE_i [1:0]. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Range [4:1] select out of bounds on signal `\PORT_B1_WR_BE': Setting 3 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Ignoring assignment to constant bits: old assignment: { 3'x \PORT_B1_WR_BE [1] } = 4'0000 new assignment: \PORT_B1_WR_BE [1] = 1'0. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Range [3:0] select out of bounds on signal `\PORT_B1_WR_BE': Setting 2 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Ignoring assignment to constant bits: old assignment: { 2'x \PORT_B1_WR_BE } = \PORT_B1_WR_BE_i new assignment: \PORT_B1_WR_BE = \PORT_B1_WR_BE_i [1:0]. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Range [36:17] select out of bounds on signal `\PORT_A1_WDATA': Setting 19 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Ignoring assignment to constant bits: old assignment: { 19'x \PORT_A1_WDATA [17] } = 20'00000000000000000000 new assignment: \PORT_A1_WDATA [17] = 1'0. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_WDATA': Setting 18 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Ignoring assignment to constant bits: old assignment: { 18'x \PORT_A1_WDATA } = \PORT_A1_WR_DATA_i new assignment: \PORT_A1_WDATA = \PORT_A1_WR_DATA_i [17:0]. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Range [36:17] select out of bounds on signal `\PORT_B1_WDATA': Setting 19 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Ignoring assignment to constant bits: old assignment: { 19'x \PORT_B1_WDATA [17] } = 20'00000000000000000000 new assignment: \PORT_B1_WDATA [17] = 1'0. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_WDATA': Setting 18 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Ignoring assignment to constant bits: old assignment: { 18'x \PORT_B1_WDATA } = \PORT_B1_WR_DATA_i new assignment: \PORT_B1_WDATA = \PORT_B1_WR_DATA_i [17:0]. Passed opt-opt_lut_ins.ys Test: mem2reg_bounds_tern -> ok xprop_eq_5s3_2: ok xprop_eq_5s3_2: ok [44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed nanoxplore-tribuf.ys Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. Passed opt-opt_lut.ys Passed opt-opt_lut_port.ys Test: t_sp_init_x_x -> ok make -C tests/techmap -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/techmap' Test: t_sp_old_auto_be -> ok xprop_ne_5u3_2: ok xprop_ne_5u3_2: ok Test: module_scope -> ok Warning: wire '\Q' is assigned in a block at < ok Test: t_sp_init_x_x_re -> ok K[45]Passed ice40-mul.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed xilinx-add_sub.ys Test: t_sp_init_x_x_ce -> ok K[46]Passed ice40-latches.ys Test: code_verilog_tutorial_good_code -> ok Passed opt-opt_mem_priority.ys Test: t_sp_init_0_x -> ok . Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::udivmod (mod): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sdivmod (div): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sdivmod (mod): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. + ../../yosys -p 'read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc' xprop_ne_5s3_2: ok xprop_ne_5s3_2: ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc' -- 1. Executing Verilog-2005 frontend: test_unconnected_output.v Parsing Verilog input from `test_unconnected_output.v' to AST representation. Generating RTLIL representation for module `\blackbox'. Generating RTLIL representation for module `\unconnected_output'. test_unconnected_output.v:19: Warning: Identifier `\clock' is implicitly declared. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Warning: Ignoring boxed module blackbox. Optimizing module unconnected_output. Test: code_verilog_tutorial_if_else -> ok 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. Warning: Ignoring boxed module blackbox. root of 1 design levels: unconnected_output Automatically selected unconnected_output as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \unconnected_output 3.1.3. Analyzing design hierarchy.. Top module: \unconnected_output Removed 0 unused modules. Warning: Resizing cell port unconnected_output.bb.out1 from 1 bits to 8 bits. 3.2. Executing FLATTEN pass (flatten design). 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Warning: Ignoring boxed module blackbox. Optimizing module unconnected_output. Warnings: 3 unique messages, 5 total End of script. Logfile hash: 5ce3cff38f, CPU: user 0.03s system 0.01s, MEM: 28.60 MB peak Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 33% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ... + cc -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. Passed xilinx-bug1460.ys Test: t_sp_init_0_x_re -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed techmap-aigmap.ys make -C tests/various -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/various' Warning: Resizing cell port mac.$mul$< ok [47]Passed qlf_k6n10f-mux.ys Test: t_sp_init_0_0 -> ok xprop_eqx_5u3_2: ok xprop_eqx_5u3_2: ok Warning: Resizing cell port TB.uut.data_out from 8 bits to 32 bits. Warning: Resizing cell port TB.uut.address_in_r from 10 bits to 8 bits. Test: code_verilog_tutorial_mux_21 -> ok Test: mem2reg -> ok Passed ice40-rom.ys Passed techmap-abc9.ys Test: module_scope_func -> ok make -C tests/verilog -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/verilog' Warning: Resizing cell port top.s0.f.j from 2 bits to 1 bits. Passed techmap-autopurge.ys < ok Passed verilog-always_comb_latch_1.ys ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$< ok Passed verilog-always_comb_nolatch_1.ys Passed ice40-macc.ys Passed opt-opt_merge_basic.ys Passed verilog-always_comb_nolatch_2.ys Passed verilog-always_comb_nolatch_3.ys Passed opt-opt_merge_init.ys Passed verilog-always_comb_nolatch_4.ys Passed opt-opt_merge_keep.ys Passed verilog-always_comb_nolatch_5.ys Passed verilog-always_comb_nolatch_6.ys Test: t_sp_init_0_any -> ok Passed verilog-asgn_expr.ys Passed various-abc9.ys < ok Passed verilog-asgn_expr_not_proc_4.ys Passed opt-opt_pow.ys Warning: reg '\Q' is assigned in a continuous assignment at < ok Passed various-aiger_dff.ys Passed opt-opt_reduce_demux.ys ...passed tests in tests/cxxrtl Passed verilog-assign_to_reg.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver. Passed verilog-atom_type_signedness.ys < ok Warning: Wire top.\t is used but has no driver. Warning: Wire top.\in is used but has no driver. Passed verilog-bug656.ys Passed various-attrib05_port_conn.ys Test: t_sp_init_v_x -> ok < ok Passed verilog-conflict_cell_memory.ys Passed various-autoname.ys < ok < ok Passed various-bug1531.ys Passed verilog-const_arst.ys Passed opt-opt_rmdff.ys Passed various-bug1614.ys Warning: Complex async reset for dff `\q'. Warning: Wire TB.\rq_b [35] is used but has no driver. Warning: Wire TB.\rq_b [34] is used but has no driver. Warning: Wire TB.\rq_b [33] is used but has no driver. Warning: Wire TB.\rq_b [32] is used but has no driver. Warning: Wire TB.\rq_b [31] is used but has no driver. Warning: Wire TB.\rq_b [30] is used but has no driver. Warning: Wire TB.\rq_b [29] is used but has no driver. Warning: Wire TB.\rq_b [28] is used but has no driver. Warning: Wire TB.\rq_b [27] is used but has no driver. Warning: Wire TB.\rq_b [26] is used but has no driver. Warning: Wire TB.\rq_b [25] is used but has no driver. Warning: Wire TB.\rq_b [24] is used but has no driver. Warning: Wire TB.\rq_b [23] is used but has no driver. Warning: Wire TB.\rq_b [22] is used but has no driver. Warning: Wire TB.\rq_b [21] is used but has no driver. Warning: Wire TB.\rq_b [20] is used but has no driver. Warning: Wire TB.\rq_b [19] is used but has no driver. Warning: Wire TB.\rq_b [18] is used but has no driver. Warning: Wire TB.\rq_b [17] is used but has no driver. Warning: Wire TB.\rq_b [16] is used but has no driver. Warning: Wire TB.\rq_b [15] is used but has no driver. Warning: Wire TB.\rq_b [14] is used but has no driver. Warning: Wire TB.\rq_b [13] is used but has no driver. Warning: Wire TB.\rq_b [12] is used but has no driver. Warning: Wire TB.\rq_b [11] is used but has no driver. Warning: Wire TB.\rq_b [10] is used but has no driver. Warning: Wire TB.\rq_b [9] is used but has no driver. Warning: Wire TB.\rq_b [8] is used but has no driver. Warning: Wire TB.\rq_b [7] is used but has no driver. Warning: Wire TB.\rq_b [6] is used but has no driver. Warning: Wire TB.\rq_b [5] is used but has no driver. Warning: Wire TB.\rq_b [4] is used but has no driver. Warning: Wire TB.\rq_b [3] is used but has no driver. Warning: Wire TB.\rq_b [2] is used but has no driver. Warning: Wire TB.\rq_b [1] is used but has no driver. Warning: Wire TB.\rq_b [0] is used but has no driver. Passed various-bug1710.ys Test: t_sp_init_v_0 -> ok Passed verilog-const_sr.ys < ok Passed various-bug1876.ys < ok Passed xilinx-bug3670.ys < ok Passed xilinx-bug1480.ys Test: t_sp_init_v_0_re -> ok Passed various-bug3879.ys Test: code_verilog_tutorial_simple_if -> ok Passed verilog-for_decl_shadow.ys Passed various-bug4082.ys < ok Passed opt-opt_share_extend.ys xprop_nex_5s3_2: ok xprop_nex_5s3_2: ok Passed verilog-func_task_arg_copying.ys Warning: found logic loop in module top: cell $xor$< Y[0] wire \ripple [0] source: < ok Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [35] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [34] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [33] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [32] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [31] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [30] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [29] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [28] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [27] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [26] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [25] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [24] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [23] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [22] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [21] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [20] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [19] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [18] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [17] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [16] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [15] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [14] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [13] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [12] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [11] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [10] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [9] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [8] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [7] is used but has no driver. Passed verilog-func_tern_hint.ys Passed verilog-func_typename_ret.ys Passed various-check.ys Passed opt-opt_share_large_pmux_cat.ys Test: muxtree -> ok Test: code_verilog_tutorial_task_global -> ok Warning: found logic loop in module pingpong: cell $memrd$\mem$< DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[2] wire \y1 [2] source: < DATA[3] wire \y2 [3] source: < DATA[2] wire \y1 [2] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[3] wire \y1 [3] source: < DATA[3] wire \y2 [3] source: < DATA[3] wire \y1 [3] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[2] wire \y2 [2] source: < DATA[0] wire \y1 [0] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[0] wire \y1 [0] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[2] wire \y1 [2] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[2] wire \y1 [2] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[3] wire \y1 [3] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[3] wire \y1 [3] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[0] wire \y1 [0] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[0] wire \y1 [0] source: < ok KWarning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed opt-opt_share_large_pmux_multipart.ys Test: t_sp_init_v_any_re -> ok Warning: found logic loop in module top: cell $auto$memory_dff.cc:512:handle_rd_port$62 ($logic_not) A[0] --> Y[0] cell $memrd$\mem$< DATA[0] wire \data [0] source: < ok Test: named_genblk -> ok Passed techmap-bug2321.ys Test: code_verilog_tutorial_v2k_reg -> ok Passed opt-opt_share_large_pmux_part.ys Passed opt-opt_share_mux_tree.ys Warning: Resizing cell port top.inst.i from 32 bits to 4 bits. Warning: Resizing cell port top.inst2.a from 32 bits to 4 bits. Warning: Resizing cell port top.inst1.a from 32 bits to 4 bits. Test: nested_genblk_resolve -> ok xprop_ge_5u3_2: ok xprop_ge_5u3_2: ok Warning: No SAT model available for cell $auto$rename.cc:501:execute$73_gold (bb). Warning: No SAT model available for cell $auto$rename.cc:501:execute$74_gold (bb). Warning: No SAT model available for cell $auto$rename.cc:501:execute$75_gold (bb). KPassed opt-opt_hier.tcl make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/opt' ...passed tests in tests/opt make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/fsm' ...passed tests in tests/fsm Warning: wire '\a_q' is assigned in a block at < ok ERROR: Cannot use both -assert2assume and -assert2cover. Expected error pattern 'Cannot use both' found !!! Passed various-chformal_check.ys Passed techmap-bug2332.ys Test: code_verilog_tutorial_which_clock -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/asicworld' ...passed tests in tests/asicworld Test: omsp_dbg_uart -> ok Passed verilog-genblk_case.ys Test: t_sp_arst_x_x_re -> ok Passed nanoxplore-add_sub.ys Warning: Complex async reset for dff `\Q'. Test: t_sp_arst_0_x -> ok Passed various-celledges_shift.ys Passed ice40-tribuf.ys Passed various-chformal_coverenable.ys Passed various-const_arg_loop.ys xprop_ge_5s3_2: ok xprop_ge_5s3_2: ok Test: t_sp_arst_0_x_re -> ok Test: t_sp_arst_0_0 -> ok Passed techmap-bug2759.ys Passed various-const_func.ys Test: multiplier -> ok Passed various-const_func_block_var.ys Warning: Drivers conflicting with a constant 1'1 driver: module input A[0] Warning: Drivers conflicting with a constant 1'1 driver: port Y[0] of cell some_buffer (buffer) Warning: reg '\Q' is assigned in a continuous assignment at < ok Passed various-cutpoint_blackbox.ys Test: t_sp_arst_0_0_re -> ok Passed various-cutpoint_whole.ys Passed various-deminout_unused.ys Passed various-design.ys ERROR: No saved design 'foo' found! Expected error pattern 'No saved design 'foo' found!' found !!! Passed various-design1.ys ERROR: No saved design 'foo' found! Expected error pattern 'No saved design 'foo' found!' found !!! Passed various-design2.ys Passed ice40-spram.ys Test: t_sp_arst_0_any_re -> ok Test: muxtree -> ok Test: t_sp_arst_0_init -> ok xprop_reduce_and_3u_3: ok xprop_reduce_and_3u_3: ok elab_sys_tasks.sv:8: Warning: X is 1. elab_sys_tasks.sv:22: Warning: Passed various-elab_sys_tasks.ys Warning: Resizing cell port cas.$mul$< ok xprop_reduce_or_3u_3: ok xprop_reduce_or_3u_3: ok Passed ice40-mux.ys Passed techmap-bug2972.ys Passed xilinx-bug1605.ys < ok Passed xilinx-bug1598.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. Passed techmap-booth.ys Passed techmap-cellmatch.ys Warning: Drivers conflicting with a constant 1'0 driver: module input PORT_A1_WR_BE_i[1] module input PORT_A1_WR_DATA_i[17] module input PORT_B1_WR_BE_i[1] module input PORT_B1_WR_DATA_i[17] Test: t_sp_arst_v_x_re -> ok Passed techmap-cellname.ys Test: t_sp_arst_v_0 -> ok Test: named_genblk -> ok Test: t_sp_arst_v_0_re -> ok < ok Passed techmap-clockgate.ys xprop_reduce_or_3s_3: ok xprop_reduce_or_3s_3: ok Passed various-equiv_assume.ys Test: nested_genblk_resolve -> ok Test: t_sp_arst_v_any -> ok < ok xprop_reduce_xor_3u_3: ok xprop_reduce_xor_3u_3: ok Test: omsp_dbg_uart -> ok Passed techmap-constmap.ys Warning: wire '\Q' is assigned in a block at < ok Passed techmap-cmp2lcu.ys Passed techmap-dffinit.ys Test: t_sp_arst_v_init_re -> ok Test: paramods -> ok Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 Passed techmap-dfflegalize_adff.ys Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff0 Test: t_sp_arst_e_x -> ok Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff0 xprop_reduce_xor_3s_3: ok xprop_reduce_xor_3s_3: ok Passed nexus-mul.ys Test: t_sp_arst_e_x_re -> ok Passed xilinx-counter.ys Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff0 Passed xilinx-dsp_fastfir.ys Passed techmap-dfflegalize_adff_init.ys Test: t_sp_arst_e_0 -> ok Passed techmap-dfflegalize_adlatch.ys Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff0 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff0 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff0 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff0 Passed techmap-dfflegalize_adlatch_init.ys xprop_reduce_xnor_3u_3: ok xprop_reduce_xnor_3u_3: ok Test: t_sp_arst_e_0_re -> ok Passed techmap-dfflegalize_aldff.ys Passed verilog-genvar_loop_decl_1.ys Passed ice40-bug1644.ys Test: t_sp_arst_e_any -> ok Passed techmap-dfflegalize_aldff_init.ys Passed microchip-dff.ys xprop_reduce_xnor_3s_3: ok xprop_reduce_xnor_3s_3: ok Passed various-equiv_make_make_assert.ys xprop_reduce_bool_1u_1: ok xprop_reduce_bool_1u_1: ok /home/buildozer/aports/testing/yosys/src/share/simcells.v:476: Warning: Yosys has only limited support for tri-state logic at the moment. Warning: Shift register inference not yet supported for family xc3se. Passed various-equiv_opt_multiclock.ys Passed verilog-genvar_loop_decl_2.ys Passed nanoxplore-latches.ys Test: t_sp_arst_e_any_re -> ok xprop_reduce_bool_3u_3: ok xprop_reduce_bool_3u_3: ok Passed techmap-dfflegalize_dff.ys Test: t_sp_arst_e_init -> ok Test: param_attr -> ok Passed various-equiv_opt_undef.ys Test: operators -> ok Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21. Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21. Passed verilog-genvar_loop_decl_3.ys Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff4 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff0 xprop_reduce_bool_3s_3: ok xprop_reduce_bool_3s_3: ok Test: t_sp_arst_e_init_re -> ok ERROR: Command stdout did have a line matching given regex "giraffe". Expected error pattern 'stdout did have a line' found !!! Passed various-exec.ys Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff4 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff0 Passed techmap-dfflegalize_dffsr.ys Passed qlf_k6n10f-meminit.ys Test: process -> ok Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. < ok Passed xilinx-opt_lut_ins.ys Test: t_sp_arst_n_x_re -> ok Passed various-fib.ys Passed nexus-mux.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nexus' Warning: Shift register inference not yet supported for family xc3se. ...passed tests in tests/arch/nexus Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff4 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff4 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff0 xprop_reduce_bool_3s_1: ok xprop_reduce_bool_3s_1: ok Test: t_sp_arst_n_0 -> ok Passed xilinx-dsp_simd.ys Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Test: t_sp_arst_n_0_re -> ok Test: paramods -> ok Passed xilinx-logic.ys Test: memory -> ok Passed verilog-ifdef_nest.ys xprop_logic_not_1u_1: ok xprop_logic_not_1u_1: ok ERROR: Unterminated preprocessor conditional! Expected error pattern 'Unterminated preprocessor conditional!' found !!! Passed verilog-ifdef_unterminated.ys Passed techmap-dfflegalize_dff_init.ys Passed techmap-dfflegalize_dlatch.ys Test: process -> ok Passed techmap-dfflegalize_dlatch_const.ys Test: t_sp_arst_n_any -> ok Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff0 [$_DFFSR_PPP_]. Test: realexpr -> ok Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff0 [$_DFFSR_PPP_]. Test: retime -> ok Test: t_sp_arst_n_any_re -> ok Passed nanoxplore-adffs.ys Test: t_sp_arst_n_init -> ok Passed techmap-dfflegalize_dlatch_init.ys Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff4 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff4 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff0 Passed various-fib_tern.ys Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff3 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff2 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff1 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff0 Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff3 [$_DFFSR_NPP_]. Test: repwhile -> ok Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff0 [$_DFFSR_PPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff0 [$_DFFSR_PPP_]. Passed techmap-dfflegalize_dffsr_init.ys Passed techmap-dfflegalize_dlatchsr.ys xprop_logic_not_3u_3: ok xprop_logic_not_3u_3: ok Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff0 Test: t_sp_arst_n_init_re -> ok Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff0 [$_DLATCHSR_PPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff0 [$_DLATCHSR_PPP_]. Test: scopes -> ok Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff3 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff2 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff1 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff0 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff3 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff2 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff1 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff0 Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff0 [$_DLATCHSR_PPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff0 [$_DLATCHSR_PPP_]. Passed techmap-dfflegalize_dlatchsr_init.ys Test: realexpr -> ok Passed gowin-lutram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gowin' ...passed tests in tests/arch/gowin Passed techmap-dfflegalize_mince.ys Test: t_sp_srst_x_x -> ok Test: operators -> ok Passed various-formalff_declockgate.ys Passed techmap-dfflegalize_inv.ys Test: t_sp_srst_x_x_re -> ok Passed techmap-dfflegalize_minsrst.ys Test: retime -> ok Test: repwhile -> ok xprop_logic_not_3s_3: ok xprop_logic_not_3s_3: ok Passed techmap-dfflegalize_sr.ys Passed verilog-incdec.ys Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff0 [$_SR_PP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff0 [$_SR_PP_]. Test: sign_part_assign -> ok Passed xilinx-xilinx_dsp.ys Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff0 [$_SR_PP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff0 [$_SR_PP_]. Test: t_sp_srst_0_x -> ok Passed techmap-dfflegalize_sr_init.ys Warning: Complex async reset for dff `\Q'. Passed various-func_port_implied_dir.ys Passed verilog-include_self.ys Passed techmap-dfflibmap.ys Warning: wire '\Q' is assigned in a block at < ok xprop_logic_not_3s_1: ok xprop_logic_not_3s_1: ok Passed techmap-dffunmap.ys Passed techmap-extractinv.ys Test: signed_full_slice -> ok < ok Passed techmap-pmux2mux.ys Test: t_sp_srst_0_0 -> ok Passed xilinx-xilinx_srl.ys Passed various-gen_if_null.ys xprop_logic_and_1u1_1: ok xprop_logic_and_1u1_1: ok Test: rotate -> ok Passed verilog-int_types.ys < ok Passed various-global_scope.ys Passed techmap-shiftx2mux.ys Passed techmap-techmap_chtype.ys Test: t_sp_srst_0_any -> ok Passed techmap-techmap_replace.ys Passed techmap-wireinit.ys Test: scopes -> ok xprop_logic_and_3u3_3: ok xprop_logic_and_3u3_3: ok Passed techmap-zinit.ys Test: sign_part_assign -> ok Passed xilinx-fsm.ys Passed various-gzip_verilog.ys Test: t_sp_srst_0_any_re -> ok Passed techmap-kogge-stone.tcl Passed various-help.ys xprop_logic_and_3s3_3: ok xprop_logic_and_3s3_3: ok Test: string_format -> ok Passed techmap-han-carlson.tcl Passed xilinx-adffs.ys Test: t_sp_srst_0_init -> ok Test: undef_eqx_nex -> ok /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: subbytes -> ok Passed techmap-sklansky.tcl Test: t_sp_srst_0_init_re -> ok Test: t_sp_srst_v_x -> ok Test: t_sp_srst_v_x_re -> ok Passed techmap-mem_simple_4x1_runtest.sh Passed techmap-recursive_runtest.sh make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/techmap' ...passed tests in tests/techmap xprop_logic_or_1u1_1: ok xprop_logic_or_1u1_1: ok Test: signed_full_slice -> ok xprop_logic_and_3s3_1: ok xprop_logic_and_3s3_1: ok < ok Passed microchip-dsp.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/microchip' ...passed tests in tests/arch/microchip Test: t_sp_srst_v_0_re -> ok Test: signedexpr -> ok Passed various-hierarchy_defer.ys Test: t_sp_srst_v_any -> ok Passed various-hierarchy_generate.ys Test: task_func -> ok Test: usb_phy_tests -> ok /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. xprop_logic_or_3u3_3: ok xprop_logic_or_3u3_3: ok Passed verilog-func_upto.ys Passed verilog-macro_arg_tromp.ys Test: t_sp_srst_v_any_re -> ok ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';' Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!! Passed verilog-macro_unapplied.ys Test: t_sp_srst_v_any_re_gated -> ok ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a' Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!! Passed verilog-macro_unapplied_newline.ys Test: t_sp_srst_v_any_ce -> ok Passed xilinx-xilinx_dffopt.ys Test: specify -> ok Passed various-hierarchy_param.ys Test: values -> ok Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. Passed xilinx-mul.ys Passed verilog-mem_bounds.ys < ok Passed verilog-package_import_separate.ys Test: verilog_primitives -> ok Test: string_format -> ok Passed verilog-package_task_func.ys Passed verilog-param_default.ys Passed verilog-param_int_types.ys Passed verilog-param_no_default.ys < ok Passed verilog-param_no_default_unbound_4.ys < ok Passed verilog-parameters_across_files.ys Passed verilog-past_signedness.ys xprop_logic_or_3s3_3: ok xprop_logic_or_3s3_3: ok Passed verilog-port_int_types.ys xprop_logic_or_3s3_1: ok xprop_logic_or_3s3_1: ok Passed verilog-prefix.ys Passed qlf_k6n10f-ioff.ys < ok xprop_shl_4u3u_3: ok xprop_shl_4u3u_3: ok < ok Warning: Module top contains RTLIL processes with sync rules. Such RTLIL processes can't always be mapped directly to Verilog always blocks. unintended changes in simulation behavior are possible! Use "proc" to convert processes to logic networks and registers. xprop_shl_4s3u_3: ok xprop_shl_4s3u_3: ok Test: subbytes -> ok Passed verilog-roundtrip_proc.ys attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033" Passed various-json_escape_chars.ys Test: t_sp_srst_e_x_re -> ok Passed verilog-sbvector.ys Test: undef_eqx_nex -> ok Warning: Resizing cell port top.u3.out from 1 bits to 2 bits. Passed various-json_scopeinfo.ys Passed verilog-sign_array_query.ys Passed xilinx-shifter.ys < ok Passed verilog-size_cast.ys Test: usb_phy_tests -> ok Passed verilog-struct_access.ys < ok Passed verilog-task_attr.ys Passed verilog-typedef_across_files.ys Passed verilog-typedef_const_shadow.ys Test: t_sp_srst_e_0_re -> ok Passed verilog-typedef_legacy_conflict.ys xprop_shr_4u3u_3: ok xprop_shr_4u3u_3: ok unbased_unsized.sv:17: Warning: Yosys has only limited support for tri-state logic at the moment. Passed verilog-unbased_unsized.ys Warning: Resizing cell port top.pt.inp from 32 bits to 64 bits. Test: t_sp_srst_e_any -> ok Passed verilog-unbased_unsized_shift.ys Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits. Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits. Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits. Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits. Passed various-keep_hierarchy.ys Test: sincos -> ok Passed various-ice40_mince_abc9.ys Test: wandwor -> ok Test: vloghammer -> ok /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: t_sp_srst_e_any_re -> ok xprop_shr_4s3u_3: ok xprop_shr_4s3u_3: ok Passed verilog-unique_if.ys Passed various-lcov.ys Test: task_func -> ok Passed verilog-unique0_if_enc.ys Test: t_sp_srst_e_init -> ok Passed verilog-unbased_unsized_tern.ys < ok ERROR: Identifier `\b' is implicitly declared. Expected error pattern 'is implicitly declared.' found !!! Passed various-logger_error.ys Test: verilog_primitives -> ok Test: arrays03 -> ok Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. Test: t_sp_srst_n_x -> ok Passed verilog-unique_if_enc.ys Passed verilog-unique_priority_if.ys ERROR: Found `else outside of macro conditional branch! Expected error pattern 'Found `else outside of macro conditional branch!' found !!! Passed verilog-unmatched_else.ys ERROR: Found `elsif outside of macro conditional branch! Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!! Passed verilog-unmatched_elsif.ys ERROR: Found `endif outside of macro conditional branch! Expected error pattern 'Found `endif outside of macro conditional branch!' found !!! Passed verilog-unmatched_endif.ys Test: t_sp_srst_n_x_re -> ok ERROR: Found `endif outside of macro conditional branch! Expected error pattern 'Found `endif outside of macro conditional branch!' found !!! Passed verilog-unmatched_endif_2.ys xprop_sshl_4s3u_3: ok xprop_sshl_4s3u_3: ok < ok Passed verilog-unnamed_genblk.ys Test: values -> ok Passed various-logger_nowarning.ys Passed verilog-unreachable_case_sign.ys Passed verilog-upto.ys Warning: wire '\b' is assigned in a block at < ok Test: t_sp_srst_n_0_re -> ok Warning: Found log message matching -W regex: Added regex 'Successfully finished Verilog frontend.' to expected warning messages list. < ok Test: t_sp_srst_n_any -> ok < ok Passed nanoxplore-mux.ys Test: wreduce -> ok xprop_shift_4u3u_3: ok xprop_shift_4u3u_3: ok Test: t_sp_srst_n_any_re -> ok xprop_shift_4s3u_3: ok xprop_shift_4s3u_3: ok Test: t_sp_srst_n_init -> ok Passed various-logic_param_simple.ys Test: t_sp_srst_n_init_re -> ok Test: t_sp_srst_gv_x_re -> ok Test: t_sp_srst_gv_x -> ok Passed various-mem2reg.ys Test: local_loop_var -> ok Test: t_sp_srst_gv_0 -> ok Test: implicit_ports -> ok Test: lesser_size_cast -> ok Test: vloghammer -> ok xprop_shift_4u2s_8: ok xprop_shift_4u2s_8: ok xprop_shift_4s2s_8: ok xprop_shift_4s2s_8: ok Test: wreduce -> ok /home/buildozer/aports/testing/yosys/src/share/simcells.v:476: Warning: Yosys has only limited support for tri-state logic at the moment. Warning: Ignoring boxed module $paramod\FDRE\INIT=1'0_$abc9_flop. Passed various-memory_word_as_index.ys Test: defvalue -> ok Test: t_sp_srst_gv_0_re -> ok Test: matching_end_labels -> ok Test: rotate -> ok xprop_shift_4u3s_3: ok xprop_shift_4u3s_3: ok Test: t_sp_srst_gv_any -> ok Test: unnamed_block_decl -> ok Test: t_sp_srst_gv_any_re -> ok Passed various-param_struct.ys Test: asgn_binop -> ok Test: memwr_port_connection -> ok Test: t_sp_srst_gv_any_re_gated -> ok Test: t_sp_srst_gv_any_ce -> ok xprop_shift_4s3s_3: ok xprop_shift_4s3s_3: ok Test: t_sp_srst_gv_any_ce_gated -> ok Passed various-peepopt_formal.ys Test: t_sp_srst_gv_init -> ok Test: partsel -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/simple' ...passed tests in tests/simple Passed various-peepopt.ys Test: t_sp_srst_gv_init_re -> ok Test: t_wren_a4d4_NO_BYTE -> ok Passed various-muxpack.ys Passed xilinx-nosrl.ys xprop_shiftx_4u2s_8: ok xprop_shiftx_4u2s_8: ok Passed various-pmux2shiftx.ys Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits. Warning: Resizing cell port act.os2.out from 3 bits to 2 bits. Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits. Warning: Resizing cell port act.os1.out from 3 bits to 1 bits. Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits. Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits. Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits. Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits. Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits. Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits. Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits. Passed various-primitives.ys Passed various-port_sign_extend.ys Passed various-printattr.ys Test: t_wren_a5d4_NO_BYTE -> ok xprop_shiftx_4u3s_3: ok xprop_shiftx_4u3s_3: ok Passed xilinx-dsp_abc9.ys xprop_mux_1: ok xprop_mux_1: ok Passed various-rand_const.ys Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21. Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18. Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22. Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16. Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17. Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70 Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68 Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63 Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61 Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58 Passed various-reg_wire_error.ys Test: t_wren_a6d4_NO_BYTE -> ok Passed xilinx-mul_unsigned.ys Passed various-muxcover.ys Passed various-rename_scramble_name.ys Test: t_wren_a3d8_NO_BYTE -> ok xprop_mux_3: ok xprop_mux_3: ok Test: macro_arg_spaces -> ok xprop_bmux_3_1: ok xprop_bmux_3_1: ok xprop_bmux_1_2: ok xprop_bmux_1_2: ok Warning: Wire top.\_e is used but has no driver. Test: t_wren_a4d8_NO_BYTE -> ok Passed various-rename_unescape.ys Test: t_wren_a4d4_W4_B4 -> ok Passed various-rename_wire_move_to_cell.ys Passed xilinx-pmgen_xilinx_srl.ys Test: t_wren_a4d8_W4_B4_separate -> ok xprop_bmux_2_2: ok xprop_bmux_2_2: ok Passed various-rtlil_signed_attribute.ys Test: t_wren_a4d8_W8_B4_separate -> ok Test: t_wren_a4d8_W8_B4 -> ok Test: t_wren_a4d8_W8_B8 -> ok xprop_demux_1_2: ok xprop_demux_1_2: ok Passed various-rtlil_z_bits.ys Test: t_wren_a4d8_W8_B8_separate -> ok Passed xilinx-latches.ys Passed various-scopeinfo.ys xprop_pmux_1_4: ok xprop_pmux_1_4: ok Passed various-scratchpad.ys xprop_pmux_2_2: ok xprop_pmux_2_2: ok Passed xilinx-mux_lut4.ys Test: t_wren_a4d2w8_W16_B4 -> ok Test: t_wren_a4d2w8_W16_B4_separate -> ok Passed various-script.ys { "creator": "Yosys 0.57 (git sha1 3aca86049e79a165932e3e7660358376f45acaed, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3)", "modules": { "top": { "attributes": { "keep": "00000000000000000000000000000001", "top": "00000000000000000000000000000001", "src": "setundef.sv:5.1-10.10" }, "ports": { "o": { "direction": "output", "bits": [ "0", "0" ] } }, "cells": { "$assert$setundef.sv:8$2": { "hide_name": 1, "type": "$assert", "parameters": { }, "attributes": { "src": "setundef.sv:8.3-8.21" }, "port_directions": { "A": "input", "EN": "input" }, "connections": { "A": [ "1" ], "EN": [ "1" ] } }, "$auto$chformal.cc:428:execute$6": { "hide_name": 1, "type": "$not", "parameters": { "A_SIGNED": "00000000000000000000000000000000", "A_WIDTH": "00000000000000000000000000000001", "Y_WIDTH": "00000000000000000000000000000001" }, "attributes": { }, "port_directions": { "A": "input", "Y": "output" }, "connections": { "A": [ "1" ], "Y": [ 2 ] } }, "$auto$chformal.cc:430:execute$8": { "hide_name": 1, "type": "$and", "parameters": { "A_SIGNED": "00000000000000000000000000000000", "A_WIDTH": "00000000000000000000000000000001", "B_SIGNED": "00000000000000000000000000000000", "B_WIDTH": "00000000000000000000000000000001", "Y_WIDTH": "00000000000000000000000000000001" }, "attributes": { }, "port_directions": { "A": "input", "B": "input", "Y": "output" }, "connections": { "A": [ 2 ], "B": [ "1" ], "Y": [ 3 ] } }, "foo": { "hide_name": 0, "type": "$scopeinfo", "parameters": { "TYPE": "module" }, "attributes": { "cell_module_not_derived": "00000000000000000000000000000001", "cell_src": "setundef.sv:6.15-6.21", "module": "$paramod\\foo\\a=2'00", "module_hdlname": "foo", "module_src": "setundef.sv:1.1-3.10" }, "port_directions": { }, "connections": { } } }, "netnames": { "$assert$setundef.sv:8$2_EN": { "hide_name": 1, "bits": [ "1" ], "attributes": { "src": "setundef.sv:8.3-8.21" } }, "$auto$rtlil.cc:2959:Not$7": { "hide_name": 1, "bits": [ 2 ], "attributes": { } }, "$auto$rtlil.cc:3006:And$9": { "hide_name": 1, "bits": [ 3 ], "attributes": { } }, "$eq$setundef.sv:8$3_Y": { "hide_name": 1, "bits": [ "1" ], "attributes": { "src": "setundef.sv:8.10-8.20" } }, "foo.o": { "hide_name": 0, "bits": [ "0", "0" ], "attributes": { "hdlname": "foo o", "src": "setundef.sv:1.47-1.48" } }, "o": { "hide_name": 0, "bits": [ "0", "0" ], "attributes": { "src": "setundef.sv:5.25-5.26" } } } } } } Passed various-setundef.ys xprop_pmux_3_1: ok xprop_pmux_3_1: ok xprop_demux_3_1: ok xprop_demux_3_1: ok Test: t_wren_a4d4w4_W16_B4 -> ok Passed various-sformatf.ys Test: t_wren_a4d4w4_W16_B4_separate -> ok Test: t_wren_a5d4w2_W16_B4_separate -> ok xprop_bwmux_1: ok xprop_bwmux_1: ok Test: t_wren_a5d4w2_W16_B4 -> ok < ok xprop_bweqx_1: ok Passed various-shregmap.ys xprop_bweqx_1: ok < ok Passed various-signext.ys xprop_ff_1: ok xprop_ff_1: ok Passed various-sim_const.ys Test: t_wren_a4d8w2_W16_B4 -> ok Test: t_wren_a5d8w1_W16_B4 -> ok Test: t_wren_a4d8w2_W16_B4_separate -> ok specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string. Test: t_wren_a5d8w1_W16_B4_separate -> ok specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string. xprop_bwmux_3: ok xprop_bwmux_3: ok Warning: No SAT model available for cell B_0 ($specrule). Warning: No SAT model available for cell C_0 ($specrule). Warning: No SAT model available for cell A_0 ($specify3). Warning: No SAT model available for cell A_0 ($specify2). Warning: No SAT model available for cell B_0 ($specify2). Passed various-specify.ys xprop_bweqx_3: ok xprop_bweqx_3: ok xprop_ff_3: ok xprop_ff_3: ok Passed various-splitnets.ys Warning: wire '\o' is assigned in a block at < ok Passed various-src.ys Test: t_wren_a5d8w2_W16_B4_separate -> ok Test: t_wren_a4d16w1_W16_B4 -> ok Warning: Critical-path does not terminate in a recognised endpoint. Warning: Cell type 'const0' not recognised! Ignoring. Passed various-sta.ys Test: t_wren_a4d16w1_W16_B4_separate -> ok Test: t_wren_a4d4w2_W8_B8_separate -> ok Test: t_wren_a4d4w2_W8_B8 -> ok Test: t_wren_a4d4w1_W8_B8 -> ok Passed various-stat.ys Passed various-stat_hierarchy.ys xprop_pmux_4_4: ok xprop_pmux_4_4: ok Test: t_wren_a4d4w1_W8_B8_separate -> ok Passed various-stat_high_level.ys xprop_dff_1pd: ok xprop_dff_1pd: ok Passed various-stat_high_level2.ys Test: t_wren_a4d8w2_W8_B8_separate -> ok Test: t_wren_a4d8w2_W8_B8 -> ok xprop_dff_1nd: ok xprop_dff_1nd: ok Test: t_wren_a3d8w2_W8_B8 -> ok Passed various-struct_access.ys Passed various-sv_defines.ys Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports. Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports. Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports. Passed various-submod_extract.ys Passed various-submod.ys ERROR: Duplicate macro arguments with name `x'. Expected error pattern 'Duplicate macro arguments with name `x'' found !!! Passed various-sv_defines_dup.ys Test: t_wren_a3d8w2_W8_B8_separate -> ok Test: t_wren_a4d4w2_W8_B4 -> ok Test: t_wren_a4d4w2_W8_B4_separate -> ok Test: t_wren_a4d2w4_W8_B4 -> ok Test: t_wren_a4d4w4_W8_B4 -> ok Test: t_wren_a4d2w4_W8_B4_separate -> ok xprop_dff_3pd: ok Test: t_wren_a4d4w4_W8_B4_separate -> ok xprop_dff_3pd: ok Test: t_wren_a4d4w4_W4_B4 -> ok xprop_dff_3nd: ok xprop_dff_3nd: ok ERROR: Mismatched brackets in macro argument: [ and }. Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!! Passed various-sv_defines_mismatch.ys ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default). Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!! Passed various-sv_defines_too_few.ys Passed various-tcl_apis.ys Passed nanoxplore-meminit.ys Test: t_wren_a4d4w4_W4_B4_separate -> ok Passed various-wrapcell.ys xprop_dffe_1pnd: ok xprop_dffe_1pnd: ok Passed various-wreduce.ys Test: t_geom_a4d64_wren -> ok Test: t_wren_a4d4w5_W4_B4_separate -> ok Test: t_wren_a4d4w5_W4_B4 -> ok Test: t_geom_a5d32_wren -> ok Passed various-wreduce2.ys Passed various-write_gzip.ys Passed various-xaiger.ys Test: t_geom_a5d64_wren -> ok xprop_dffe_1nnd: ok xprop_dffe_1nnd: ok Test: t_geom_a6d16_wren -> ok Test: t_geom_a6d30_wren -> ok Test: t_geom_a7d4_wren -> ok Test: t_geom_a6d64_wren -> ok Passed various-chparam.sh Test: t_geom_a7d6_wren -> ok Test: t_geom_a7d8_wren -> ok xprop_dffe_1ppd: ok xprop_dffe_1ppd: ok Passed various-logger_cmd_error.sh xprop_dffe_1npd: ok xprop_dffe_1npd: ok Test: t_geom_a7d17_wren -> ok Passed various-clk2fflogic_effects.sh Passed various-hierarchy.sh Test: t_geom_a9d4_wren -> ok Test: t_geom_a8d6_wren -> ok Test: t_geom_a9d8_wren -> ok Test: t_geom_a8d4_wren -> ok Passed various-logger_fail.sh Test: t_geom_a3d18_9b1B -> ok Test: t_geom_a9d5_wren -> ok Test: t_geom_a4d18_9b1B -> ok Test: t_geom_a4d4_9b1B -> ok Test: t_geom_a9d6_wren -> ok xprop_dffe_3pnd: ok xprop_dffe_3pnd: ok xprop_dffe_3nnd: ok xprop_dffe_3nnd: ok Passed various-svalways.sh Test: t_geom_a6d4_9b1B -> ok Test: t_geom_a5d32_9b1B -> ok xprop_dffe_3ppd: ok xprop_dffe_3ppd: ok Test: t_geom_a7d11_9b1B -> ok Test: t_geom_a11d1_9b1B -> ok xprop_dffe_3npd: ok xprop_dffe_3npd: ok done make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/xprop' ...passed tests in tests/xprop Test: t_geom_a7d18_9b1B -> ok Test: t_wide_sdp_a6r1w1b1x1 -> ok Test: t_wide_sdp_a8r1w1b1x1 -> ok Test: t_wide_sdp_a6r0w0b0x0 -> ok Test: t_wide_sdp_a7r1w1b1x1 -> ok Test: t_wide_sdp_a6r1w0b0x0 -> ok Test: t_wide_sdp_a6r2w0b0x0 -> ok Passed various-async.sh Test: t_wide_sdp_a6r0w1b0x0 -> ok Test: t_wide_sdp_a6r3w0b0x0 -> ok Test: t_wide_sdp_a6r0w1b1x0 -> ok Passed various-sv_implicit_ports.sh Test: t_wide_sdp_a6r4w0b0x0 -> ok Test: t_wide_sdp_a6r0w2b0x0 -> ok Test: t_wide_sdp_a6r5w0b0x0 -> ok Test: t_wide_sdp_a6r0w2b2x0 -> ok Test: t_wide_sdp_a6r0w3b2x0 -> ok Test: t_wide_sdp_a7r0w0b0x0 -> ok Test: t_wide_sdp_a6r0w4b2x0 -> ok Test: t_wide_sdp_a7r1w0b0x0 -> ok Test: t_wide_sdp_a7r0w1b0x0 -> ok Test: t_wide_sdp_a7r2w0b0x0 -> ok Test: t_wide_sdp_a7r0w1b1x0 -> ok Test: t_wide_sdp_a7r3w0b0x0 -> ok Test: t_wide_sdp_a7r0w2b2x0 -> ok Test: t_wide_sdp_a7r0w2b0x0 -> ok Test: t_wide_sdp_a7r4w0b0x0 -> ok Test: t_wide_sdp_a7r0w3b2x0 -> ok Test: t_wide_sdp_a7r5w0b0x0 -> ok Test: t_wide_sdp_a6r0w5b2x0 -> ok Test: t_wide_sp_mix_a7r1w1b1 -> ok Test: t_wide_sp_mix_a8r1w1b1 -> ok Test: t_wide_sp_mix_a6r1w1b1 -> ok Test: t_wide_sp_mix_a6r0w0b0 -> ok Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sp_mix_a6r1w0b0 -> ok Test: t_wide_sp_mix_a6r2w0b0 -> ok Test: t_wide_sdp_a7r0w5b2x0 -> ok Test: t_wide_sp_mix_a6r3w0b0 -> ok Test: t_wide_sp_mix_a6r4w0b0 -> ok Test: t_wide_sp_mix_a6r0w1b0 -> ok Test: t_wide_sp_mix_a6r0w1b1 -> ok Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. Test: t_wide_sp_mix_a6r0w2b0 -> ok Test: t_wide_sp_mix_a6r5w0b0 -> ok Test: t_wide_sp_mix_a6r0w2b2 -> ok Test: t_wide_sp_mix_a7r0w0b0 -> ok Test: t_wide_sp_mix_a7r0w1b0 -> ok Test: t_wide_sp_mix_a6r0w3b2 -> ok Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_mix_a7r3w0b0 -> ok Test: t_wide_sp_mix_a7r2w0b0 -> ok Test: t_wide_sp_mix_a7r0w1b1 -> ok Test: t_wide_sp_mix_a6r0w4b2 -> ok Test: t_wide_sp_mix_a7r4w0b0 -> ok Test: t_wide_sp_mix_a7r0w2b0 -> ok Test: t_wide_sp_mix_a7r0w2b2 -> ok Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a6r0w5b2 -> ok Test: t_wide_sp_mix_a7r0w3b2 -> ok Test: t_wide_sp_mix_a7r0w4b2 -> ok Test: t_wide_sp_tied_a6r1w1b1 -> ok Test: t_wide_sp_tied_a7r1w1b1 -> ok Test: t_wide_sp_tied_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w0b0 -> ok Test: t_wide_sp_tied_a6r2w0b0 -> ok Test: t_wide_sp_mix_a7r0w5b2 -> ok Test: t_wide_sp_tied_a6r3w0b0 -> ok Test: t_wide_sp_tied_a6r1w0b0 -> ok Test: t_wide_sp_tied_a6r0w1b1 -> ok Test: t_wide_sp_tied_a6r0w1b0 -> ok Test: t_wide_sp_tied_a6r4w0b0 -> ok Test: t_wide_sp_tied_a6r0w2b0 -> ok Test: t_wide_sp_tied_a6r0w2b2 -> ok Test: t_wide_sp_tied_a6r5w0b0 -> ok Test: t_wide_sp_tied_a6r0w3b2 -> ok Test: t_wide_sp_tied_a7r1w0b0 -> ok Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a7r2w0b0 -> ok Test: t_wide_sp_tied_a6r0w4b2 -> ok Test: t_wide_sp_tied_a7r3w0b0 -> ok Test: t_wide_sp_tied_a7r0w1b0 -> ok Test: t_wide_sp_tied_a7r4w0b0 -> ok Passed various-pmgen_reduce.ys Test: t_wide_sp_tied_a6r0w5b2 -> ok Test: t_wide_sp_tied_a7r0w1b1 -> ok Test: t_wide_sp_tied_a7r0w2b0 -> ok Test: t_wide_sp_tied_a7r5w0b0 -> ok Test: t_wide_sp_tied_a7r0w2b2 -> ok Test: t_wide_write_a7r1w1b1 -> ok Test: t_wide_read_a6r1w1b1 -> ok Test: t_wide_sp_tied_a7r0w3b2 -> ok Test: t_wide_write_a6r1w1b1 -> ok Test: t_wide_write_a6r0w0b0 -> ok Test: t_wide_read_a7r1w1b1 -> ok Test: t_wide_write_a8r1w1b1 -> ok Test: t_wide_sp_tied_a7r0w4b2 -> ok Test: t_wide_read_a6r0w0b0 -> ok Test: t_wide_read_a8r1w1b1 -> ok Test: t_wide_read_a6r1w0b0 -> ok Test: t_wide_write_a6r1w0b0 -> ok Test: t_wide_sp_tied_a7r0w5b2 -> ok Test: t_wide_read_a6r2w0b0 -> ok Test: t_wide_write_a6r2w0b0 -> ok Test: t_wide_write_a6r3w0b0 -> ok Test: t_wide_read_a6r3w0b0 -> ok Passed various-plugin.sh Test: t_wide_write_a6r0w1b0 -> ok Test: t_wide_read_a6r4w0b0 -> ok Test: t_wide_read_a6r0w1b0 -> ok Test: t_wide_write_a6r4w0b0 -> ok Test: t_wide_read_a6r5w0b0 -> ok Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_write_a6r0w1b1 -> ok Test: t_wide_read_a6r0w2b0 -> ok Test: t_wide_write_a6r5w0b0 -> ok Test: t_wide_write_a6r0w2b0 -> ok Test: t_wide_write_a6r0w2b2 -> ok Test: t_wide_read_a6r0w2b2 -> ok Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_write_a6r0w3b2 -> ok Test: t_wide_read_a6r0w4b2 -> ok Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_read_a7r0w0b0 -> ok Test: t_wide_read_a7r1w0b0 -> ok Test: t_wide_write_a7r0w0b0 -> ok Test: t_wide_read_a7r2w0b0 -> ok Test: t_wide_write_a7r1w0b0 -> ok Test: t_wide_read_a7r3w0b0 -> ok Test: t_wide_write_a7r2w0b0 -> ok Test: t_wide_write_a7r3w0b0 -> ok Test: t_wide_read_a6r0w5b2 -> ok Test: t_wide_write_a6r0w5b2 -> ok Test: t_wide_read_a7r0w1b0 -> ok Test: t_wide_read_a7r4w0b0 -> ok Test: t_wide_write_a7r4w0b0 -> ok Test: t_wide_write_a7r0w1b0 -> ok Test: t_wide_write_a7r0w1b1 -> ok Test: t_wide_read_a7r5w0b0 -> ok Test: t_wide_read_a7r0w2b0 -> ok Test: t_wide_read_a7r0w2b2 -> ok Test: t_wide_write_a7r0w2b0 -> ok Test: t_wide_read_a7r0w1b1 -> ok Test: t_wide_write_a7r5w0b0 -> ok Test: t_wide_write_a7r0w2b2 -> ok Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_read_a7r0w3b2 -> ok Test: t_quad_port_a2d2 -> ok Test: t_wide_read_a7r0w4b2 -> ok Test: t_wide_write_a7r0w4b2 -> ok Test: t_quad_port_a4d2 -> ok Test: t_quad_port_a5d2 -> ok Test: t_quad_port_a4d4 -> ok Test: t_wide_oct_a4w2r1 -> ok Test: t_wide_quad_a4w2r2 -> ok Test: t_wide_quad_a4w2r1 -> ok Test: t_quad_port_a4d8 -> ok Test: t_quad_port_a6d2 -> ok Test: t_wide_write_a7r0w5b2 -> ok Test: t_wide_oct_a4w2r2 -> ok Test: t_wide_oct_a4w2r3 -> ok Test: t_wide_quad_a4w2r3 -> ok Test: t_wide_quad_a4w2r4 -> ok Test: t_wide_oct_a4w2r4 -> ok Test: t_wide_quad_a4w2r5 -> ok Test: t_wide_read_a7r0w5b2 -> ok Test: t_wide_oct_a4w2r5 -> ok Test: t_wide_quad_a4w2r6 -> ok Test: t_wide_oct_a4w2r6 -> ok Test: t_wide_oct_a4w2r7 -> ok Test: t_wide_quad_a4w2r7 -> ok Test: t_wide_quad_a4w2r8 -> ok Test: t_wide_oct_a4w2r8 -> ok Test: t_wide_oct_a4w4r1 -> ok Test: t_wide_quad_a4w4r1 -> ok Test: t_wide_quad_a4w4r4 -> ok Test: t_wide_quad_a4w2r9 -> ok Test: t_wide_oct_a4w2r9 -> ok Test: t_wide_quad_a5w2r1 -> ok Test: t_wide_oct_a4w4r4 -> ok Test: t_wide_oct_a5w2r1 -> ok Test: t_wide_quad_a4w4r6 -> ok Test: t_wide_oct_a4w4r6 -> ok Test: t_wide_quad_a5w2r4 -> ok Test: t_wide_quad_a4w4r9 -> ok Test: t_wide_oct_a4w4r9 -> ok Test: t_wide_oct_a5w2r4 -> ok Test: t_wide_quad_a5w2r9 -> ok Passed xilinx-macc.sh Test: t_no_reset -> ok Test: t_gclken -> ok Test: t_wide_oct_a5w2r9 -> ok Passed xilinx-tribuf.sh Test: t_ungated -> ok Test: t_grden -> ok Test: t_rom_case -> ok Test: t_rom_case_block -> ok Test: t_gclken_ce -> ok Test: t_wr_byte -> ok Test: t_grden_ce -> ok Test: t_rst_wr_byte -> ok Test: t_trans_byte -> ok Test: t_exclwr -> ok Test: t_excl_rst -> ok Test: t_trans_rst -> ok Test: t_transwr -> ok Test: t_wr_rst_byte -> ok Test: t_rdenrst_wr_byte -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memlib' ...passed tests in tests/memlib Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. Passed xilinx-attributes_test.ys Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[0] --> Q[0] wire \dword [0] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[0] --> Y[0] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[0] --> Y[0] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[1] --> Q[1] wire \dword [1] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[1] --> Y[1] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[1] --> Y[1] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[2] --> Q[2] wire \dword [2] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[2] --> Y[2] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[2] --> Y[2] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[3] --> Q[3] wire \dword [3] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[3] --> Y[3] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[3] --> Y[3] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[4] --> Q[4] wire \dword [4] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[4] --> Y[4] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[4] --> Y[4] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[5] --> Q[5] wire \dword [5] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[5] --> Y[5] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[5] --> Y[5] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[6] --> Q[6] wire \dword [6] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[6] --> Y[6] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[6] --> Y[6] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[7] --> Q[7] wire \dword [7] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[7] --> Y[7] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[7] --> Y[7] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[8] --> Q[8] wire \dword [8] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[8] --> Y[8] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[8] --> Y[8] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[9] --> Q[9] wire \dword [9] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[9] --> Y[9] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[9] --> Y[9] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[10] --> Q[10] wire \dword [10] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[10] --> Y[10] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[10] --> Y[10] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[11] --> Q[11] wire \dword [11] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[11] --> Y[11] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[11] --> Y[11] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[12] --> Q[12] wire \dword [12] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[12] --> Y[12] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[12] --> Y[12] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[13] --> Q[13] wire \dword [13] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[13] --> Y[13] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[13] --> Y[13] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[14] --> Q[14] wire \dword [14] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[14] --> Y[14] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[14] --> Y[14] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[15] --> Q[15] wire \dword [15] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[15] --> Y[15] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[15] --> Y[15] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[16] --> Q[16] wire \dword [16] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[16] --> Y[16] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[16] --> Y[16] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[17] --> Q[17] wire \dword [17] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[17] --> Y[17] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[17] --> Y[17] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[18] --> Q[18] wire \dword [18] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[18] --> Y[18] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[18] --> Y[18] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[19] --> Q[19] wire \dword [19] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[19] --> Y[19] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[19] --> Y[19] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[20] --> Q[20] wire \dword [20] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[20] --> Y[20] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[20] --> Y[20] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[21] --> Q[21] wire \dword [21] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[21] --> Y[21] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[21] --> Y[21] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[22] --> Q[22] wire \dword [22] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[22] --> Y[22] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[22] --> Y[22] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[23] --> Q[23] wire \dword [23] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[23] --> Y[23] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[23] --> Y[23] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[24] --> Q[24] wire \dword [24] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[24] --> Y[24] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[24] --> Y[24] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[25] --> Q[25] wire \dword [25] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[25] --> Y[25] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[25] --> Y[25] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[26] --> Q[26] wire \dword [26] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[26] --> Y[26] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[26] --> Y[26] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[27] --> Q[27] wire \dword [27] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[27] --> Y[27] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[27] --> Y[27] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[28] --> Q[28] wire \dword [28] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[28] --> Y[28] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[28] --> Y[28] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[29] --> Q[29] wire \dword [29] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[29] --> Y[29] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[29] --> Y[29] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[30] --> Q[30] wire \dword [30] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[30] --> Y[30] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[30] --> Y[30] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[31] --> Q[31] wire \dword [31] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[31] --> Y[31] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[31] --> Y[31] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[32] --> Q[32] wire \dword [32] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[32] --> Y[32] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[32] --> Y[32] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[33] --> Q[33] wire \dword [33] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[33] --> Y[33] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[33] --> Y[33] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[34] --> Q[34] wire \dword [34] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[34] --> Y[34] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[34] --> Y[34] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[35] --> Q[35] wire \dword [35] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[35] --> Y[35] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[35] --> Y[35] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[36] --> Q[36] wire \dword [36] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[36] --> Y[36] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[36] --> Y[36] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[37] --> Q[37] wire \dword [37] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[37] --> Y[37] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[37] --> Y[37] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[38] --> Q[38] wire \dword [38] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[38] --> Y[38] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[38] --> Y[38] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[39] --> Q[39] wire \dword [39] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[39] --> Y[39] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[39] --> Y[39] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[40] --> Q[40] wire \dword [40] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[40] --> Y[40] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[40] --> Y[40] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[41] --> Q[41] wire \dword [41] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[41] --> Y[41] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[41] --> Y[41] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[42] --> Q[42] wire \dword [42] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[42] --> Y[42] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[42] --> Y[42] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[43] --> Q[43] wire \dword [43] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[43] --> Y[43] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[43] --> Y[43] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[44] --> Q[44] wire \dword [44] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[44] --> Y[44] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[44] --> Y[44] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[45] --> Q[45] wire \dword [45] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[45] --> Y[45] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[45] --> Y[45] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[46] --> Q[46] wire \dword [46] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[46] --> Y[46] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[46] --> Y[46] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[47] --> Q[47] wire \dword [47] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[47] --> Y[47] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[47] --> Y[47] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[48] --> Q[48] wire \dword [48] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[48] --> Y[48] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[48] --> Y[48] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[49] --> Q[49] wire \dword [49] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[49] --> Y[49] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[49] --> Y[49] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[50] --> Q[50] wire \dword [50] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[50] --> Y[50] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[50] --> Y[50] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[51] --> Q[51] wire \dword [51] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[51] --> Y[51] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[51] --> Y[51] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[52] --> Q[52] wire \dword [52] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[52] --> Y[52] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[52] --> Y[52] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[53] --> Q[53] wire \dword [53] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[53] --> Y[53] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[53] --> Y[53] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[54] --> Q[54] wire \dword [54] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[54] --> Y[54] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[54] --> Y[54] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[55] --> Q[55] wire \dword [55] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[55] --> Y[55] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[55] --> Y[55] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[56] --> Q[56] wire \dword [56] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[56] --> Y[56] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[56] --> Y[56] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[57] --> Q[57] wire \dword [57] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[57] --> Y[57] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[57] --> Y[57] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[58] --> Q[58] wire \dword [58] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[58] --> Y[58] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[58] --> Y[58] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[59] --> Q[59] wire \dword [59] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[59] --> Y[59] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[59] --> Y[59] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[60] --> Q[60] wire \dword [60] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[60] --> Y[60] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[60] --> Y[60] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[61] --> Q[61] wire \dword [61] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[61] --> Y[61] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[61] --> Y[61] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[62] --> Q[62] wire \dword [62] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[62] --> Y[62] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[62] --> Y[62] Warning: found logic loop in module latch_002_gate: cell $auto$proc_dlatch.cc:432:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[63] --> Q[63] wire \dword [63] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[63] --> Y[63] cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[63] --> Y[63] Passed xilinx-dffs.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. Passed various-dynamic_part_select.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/various' ...passed tests in tests/various Passed xilinx-mux.ys Passed xilinx-asym_ram_sdp.ys Passed nanoxplore-lutram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nanoxplore' ...passed tests in tests/arch/nanoxplore Passed ecp5-memories.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ecp5' ...passed tests in tests/arch/ecp5 Warning: Resizing cell port TB.uut.address_in_w from 11 bits to 10 bits. Warning: Resizing cell port TB.uut.data_in from 18 bits to 36 bits. Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. Passed qlf_k6n10f-t_mem3.ys Passed qlf_k6n10f-t_mem4.ys Passed qlf_k6n10f-t_mem2.ys Passed qlf_k6n10f-t_mem5.ys Passed xilinx-abc9_dff.ys Passed qlf_k6n10f-t_mem1.ys Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. Passed qlf_k6n10f-t_mem6.ys Warning: Resizing cell port TB.uut.address_in_w from 10 bits to 8 bits. Warning: Resizing cell port TB.uut.data_in from 8 bits to 32 bits. Test: partsel -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/simple_abc9' ...passed tests in tests/simple_abc9 Warning: Shift register inference not yet supported for family xc3s. Passed xilinx-dsp_cascade.ys Warning: Resizing cell port sp_read_or_write.mem.0.0.BWE_A from 8 bits to 9 bits. Warning: Resizing cell port sp_read_or_write.mem.0.0.BWE_B from 8 bits to 9 bits. Passed xilinx-priority_memory.ys Passed xilinx-lutram.ys Warning: Resizing cell port TB.uut.data_out from 18 bits to 36 bits. Warning: Resizing cell port TB.uut.address_in_r from 11 bits to 10 bits. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [17] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [16] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [15] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [14] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [13] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [12] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [11] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [10] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [9] is used but has no driver. Warning: Wire TB.$auto$wreduce.cc:514:run$140528 [8] is used but has no driver. Passed qlf_k6n10f-t_mem0.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/qlf_k6n10f' ...passed tests in tests/arch/quicklogic/qlf_k6n10f Passed verilog-dynamic_range_lhs.sh make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/verilog' ...passed tests in tests/verilog Passed xilinx-blockram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/xilinx' ...passed tests in tests/arch/xilinx Passed ice40-memories.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ice40' ...passed tests in tests/arch/ice40 Passed "make test". rm tests/sat/run-test.mk tests/arch/quicklogic/pp3/run-test.mk tests/arch/efinix/run-test.mk tests/arch/anlogic/run-test.mk tests/arch/microchip/run-test.mk tests/arch/ice40/run-test.mk tests/bugpoint/run-test.mk tests/arch/gowin/run-test.mk tests/arch/machxo2/run-test.mk tests/arch/quicklogic/qlf_k6n10f/run-test.mk tests/opt/run-test.mk tests/arch/intel_alm/run-test.mk tests/various/run-test.mk tests/arch/nanoxplore/run-test.mk tests/verilog/run-test.mk tests/arch/nexus/run-test.mk tests/sim/run-test.mk tests/arch/gatemate/run-test.mk tests/arch/ecp5/run-test.mk tests/svtypes/run-test.mk tests/arch/xilinx/run-test.mk tests/techmap/run-test.mk >>> yosys: Entering fakeroot... [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] ENABLE_ABC:=1 mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc yosys-witness /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin if [ -n "strip" ]; then strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys; fi if [ -n "strip" ]; then strip /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys-filterlib; fi mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys cp -r share/. /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys/. mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/ if [ -n "strip" ]; then strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/libyosys.so; fi mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/libyosys.so cp -r share /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys cp misc/__init__.py /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/ '/home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/libyosys.so' -> '/usr/lib/yosys/libyosys.so' >>> yosys-dev*: Running split function dev... 'usr/bin/yosys-config' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/usr/bin/yosys-config' './usr/share/yosys/include' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/./usr/share/yosys/include' './usr/lib/python3.12/site-packages/pyosys/share/include' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/./usr/lib/python3.12/site-packages/pyosys/share/include' >>> yosys-dev*: Preparing subpackage yosys-dev... >>> yosys-dev*: Stripping binaries >>> yosys-dev*: Running postcheck for yosys-dev >>> py3-yosys*: Running split function py3... 'usr/lib/python3.12' -> '/home/buildozer/aports/testing/yosys/pkg/py3-yosys/usr/lib/python3.12' >>> py3-yosys*: Preparing subpackage py3-yosys... >>> py3-yosys*: Running postcheck for py3-yosys >>> yosys*: Running postcheck for yosys >>> yosys*: Preparing package yosys... >>> yosys*: Stripping binaries >>> yosys*: Scanning shared objects >>> yosys-dev*: Scanning shared objects >>> py3-yosys*: Tracing dependencies... python3 yosys=0.57-r0 python3~3.12 yosys=0.57-r0 >>> py3-yosys*: Package size: 7.6 MB >>> py3-yosys*: Compressing data... >>> py3-yosys*: Create checksum... >>> py3-yosys*: Create py3-yosys-0.57-r0.apk >>> yosys-dev*: Tracing dependencies... python3~3.12 >>> yosys-dev*: Package size: 1.2 MB >>> yosys-dev*: Compressing data... >>> yosys-dev*: Create checksum... >>> yosys-dev*: Create yosys-dev-0.57-r0.apk >>> yosys*: Tracing dependencies... abc so:libboost_filesystem.so.1.84.0 so:libboost_python312.so.1.84.0 so:libc.musl-x86_64.so.1 so:libffi.so.8 so:libgcc_s.so.1 so:libpython3.12.so.1.0 so:libreadline.so.8 so:libstdc++.so.6 so:libtcl8.6.so so:libz.so.1 >>> yosys*: Package size: 68.2 MB >>> yosys*: Compressing data... >>> yosys*: Create checksum... >>> yosys*: Create yosys-0.57-r0.apk >>> yosys: Build complete at Fri, 24 Oct 2025 21:50:05 +0000 elapsed time 0h 7m 31s >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Uninstalling dependencies... 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OK: 441 MiB in 107 packages >>> yosys: Updating the testing/x86_64 repository index... >>> yosys: Signing the index...