/*
 * Copyright (c) 2025, Mediatek Inc. All rights reserved
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef MT6373_LOWPOWER_REG_H
#define MT6373_LOWPOWER_REG_H

#define MT6373_RG_BUCK_VBUCK0_VOSEL_SLEEP_ADDR		0x1487
#define MT6373_RG_BUCK_VBUCK0_ONLV_EN_ADDR		0x1488
#define MT6373_RG_BUCK_VBUCK0_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK0_RC0_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC1_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC2_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC3_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC4_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC5_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC6_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC7_OP_EN_ADDR		0x148D
#define MT6373_RG_BUCK_VBUCK0_RC8_OP_EN_ADDR		0x148E
#define MT6373_RG_BUCK_VBUCK0_RC9_OP_EN_ADDR		0x148E
#define MT6373_RG_BUCK_VBUCK0_RC10_OP_EN_ADDR		0x148E
#define MT6373_RG_BUCK_VBUCK0_RC11_OP_EN_ADDR		0x148E
#define MT6373_RG_BUCK_VBUCK0_RC12_OP_EN_ADDR		0x148E
#define MT6373_RG_BUCK_VBUCK0_RC13_OP_EN_ADDR		0x148E
#define MT6373_RG_BUCK_VBUCK0_HW0_OP_EN_ADDR		0x148F
#define MT6373_RG_BUCK_VBUCK0_HW1_OP_EN_ADDR		0x148F
#define MT6373_RG_BUCK_VBUCK0_HW2_OP_EN_ADDR		0x148F
#define MT6373_RG_BUCK_VBUCK0_HW3_OP_EN_ADDR		0x148F
#define MT6373_RG_BUCK_VBUCK0_SW_OP_EN_ADDR		0x148F
#define MT6373_RG_BUCK_VBUCK0_RC0_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC1_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC2_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC3_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC4_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC5_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC6_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC7_OP_CFG_ADDR		0x1490
#define MT6373_RG_BUCK_VBUCK0_RC8_OP_CFG_ADDR		0x1491
#define MT6373_RG_BUCK_VBUCK0_RC9_OP_CFG_ADDR		0x1491
#define MT6373_RG_BUCK_VBUCK0_RC10_OP_CFG_ADDR		0x1491
#define MT6373_RG_BUCK_VBUCK0_RC11_OP_CFG_ADDR		0x1491
#define MT6373_RG_BUCK_VBUCK0_RC12_OP_CFG_ADDR		0x1491
#define MT6373_RG_BUCK_VBUCK0_RC13_OP_CFG_ADDR		0x1491
#define MT6373_RG_BUCK_VBUCK0_HW0_OP_CFG_ADDR		0x1492
#define MT6373_RG_BUCK_VBUCK0_HW1_OP_CFG_ADDR		0x1492
#define MT6373_RG_BUCK_VBUCK0_HW2_OP_CFG_ADDR		0x1492
#define MT6373_RG_BUCK_VBUCK0_HW3_OP_CFG_ADDR		0x1492
#define MT6373_RG_BUCK_VBUCK0_RC0_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC1_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC2_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC3_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC4_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC5_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC6_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC7_OP_MODE_ADDR		0x1493
#define MT6373_RG_BUCK_VBUCK0_RC8_OP_MODE_ADDR		0x1494
#define MT6373_RG_BUCK_VBUCK0_RC9_OP_MODE_ADDR		0x1494
#define MT6373_RG_BUCK_VBUCK0_RC10_OP_MODE_ADDR		0x1494
#define MT6373_RG_BUCK_VBUCK0_RC11_OP_MODE_ADDR		0x1494
#define MT6373_RG_BUCK_VBUCK0_RC12_OP_MODE_ADDR		0x1494
#define MT6373_RG_BUCK_VBUCK0_RC13_OP_MODE_ADDR		0x1494
#define MT6373_RG_BUCK_VBUCK0_HW0_OP_MODE_ADDR		0x1495
#define MT6373_RG_BUCK_VBUCK0_HW1_OP_MODE_ADDR		0x1495
#define MT6373_RG_BUCK_VBUCK0_HW2_OP_MODE_ADDR		0x1495
#define MT6373_RG_BUCK_VBUCK0_HW3_OP_MODE_ADDR		0x1495
#define MT6373_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR		0x1507
#define MT6373_RG_BUCK_VBUCK1_ONLV_EN_ADDR		0x1508
#define MT6373_RG_BUCK_VBUCK1_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR		0x150D
#define MT6373_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR		0x150E
#define MT6373_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR		0x150E
#define MT6373_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR		0x150E
#define MT6373_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR		0x150E
#define MT6373_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR		0x150E
#define MT6373_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR		0x150E
#define MT6373_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR		0x150F
#define MT6373_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR		0x150F
#define MT6373_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR		0x150F
#define MT6373_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR		0x150F
#define MT6373_RG_BUCK_VBUCK1_SW_OP_EN_ADDR		0x150F
#define MT6373_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR		0x1510
#define MT6373_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR		0x1511
#define MT6373_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR		0x1511
#define MT6373_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR		0x1511
#define MT6373_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR		0x1511
#define MT6373_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR		0x1511
#define MT6373_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR		0x1511
#define MT6373_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR		0x1512
#define MT6373_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR		0x1512
#define MT6373_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR		0x1512
#define MT6373_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR		0x1512
#define MT6373_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR		0x1513
#define MT6373_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR		0x1514
#define MT6373_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR		0x1514
#define MT6373_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR		0x1514
#define MT6373_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR		0x1514
#define MT6373_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR		0x1514
#define MT6373_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR		0x1514
#define MT6373_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR		0x1515
#define MT6373_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR		0x1515
#define MT6373_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR		0x1515
#define MT6373_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR		0x1515
#define MT6373_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR		0x1587
#define MT6373_RG_BUCK_VBUCK2_ONLV_EN_ADDR		0x1588
#define MT6373_RG_BUCK_VBUCK2_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR		0x158D
#define MT6373_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR		0x158E
#define MT6373_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR		0x158E
#define MT6373_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR		0x158E
#define MT6373_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR		0x158E
#define MT6373_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR		0x158E
#define MT6373_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR		0x158E
#define MT6373_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR		0x158F
#define MT6373_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR		0x158F
#define MT6373_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR		0x158F
#define MT6373_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR		0x158F
#define MT6373_RG_BUCK_VBUCK2_SW_OP_EN_ADDR		0x158F
#define MT6373_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR		0x1590
#define MT6373_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR		0x1591
#define MT6373_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR		0x1591
#define MT6373_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR		0x1591
#define MT6373_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR		0x1591
#define MT6373_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR		0x1591
#define MT6373_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR		0x1591
#define MT6373_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR		0x1592
#define MT6373_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR		0x1592
#define MT6373_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR		0x1592
#define MT6373_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR		0x1592
#define MT6373_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR		0x1593
#define MT6373_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR		0x1594
#define MT6373_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR		0x1594
#define MT6373_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR		0x1594
#define MT6373_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR		0x1594
#define MT6373_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR		0x1594
#define MT6373_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR		0x1594
#define MT6373_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR		0x1595
#define MT6373_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR		0x1595
#define MT6373_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR		0x1595
#define MT6373_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR		0x1595
#define MT6373_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR		0x1607
#define MT6373_RG_BUCK_VBUCK3_ONLV_EN_ADDR		0x1608
#define MT6373_RG_BUCK_VBUCK3_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR		0x160D
#define MT6373_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR		0x160E
#define MT6373_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR		0x160E
#define MT6373_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR		0x160E
#define MT6373_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR		0x160E
#define MT6373_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR		0x160E
#define MT6373_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR		0x160E
#define MT6373_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR		0x160F
#define MT6373_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR		0x160F
#define MT6373_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR		0x160F
#define MT6373_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR		0x160F
#define MT6373_RG_BUCK_VBUCK3_SW_OP_EN_ADDR		0x160F
#define MT6373_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR		0x1610
#define MT6373_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR		0x1611
#define MT6373_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR		0x1611
#define MT6373_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR		0x1611
#define MT6373_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR		0x1611
#define MT6373_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR		0x1611
#define MT6373_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR		0x1611
#define MT6373_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR		0x1612
#define MT6373_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR		0x1612
#define MT6373_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR		0x1612
#define MT6373_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR		0x1612
#define MT6373_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR		0x1613
#define MT6373_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR		0x1614
#define MT6373_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR		0x1614
#define MT6373_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR		0x1614
#define MT6373_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR		0x1614
#define MT6373_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR		0x1614
#define MT6373_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR		0x1614
#define MT6373_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR		0x1615
#define MT6373_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR		0x1615
#define MT6373_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR		0x1615
#define MT6373_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR		0x1615
#define MT6373_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR		0x1687
#define MT6373_RG_BUCK_VBUCK4_ONLV_EN_ADDR		0x1688
#define MT6373_RG_BUCK_VBUCK4_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR		0x168D
#define MT6373_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR		0x168E
#define MT6373_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR		0x168E
#define MT6373_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR		0x168E
#define MT6373_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR		0x168E
#define MT6373_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR		0x168E
#define MT6373_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR		0x168E
#define MT6373_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR		0x168F
#define MT6373_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR		0x168F
#define MT6373_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR		0x168F
#define MT6373_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR		0x168F
#define MT6373_RG_BUCK_VBUCK4_SW_OP_EN_ADDR		0x168F
#define MT6373_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR		0x1690
#define MT6373_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR		0x1691
#define MT6373_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR		0x1691
#define MT6373_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR		0x1691
#define MT6373_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR		0x1691
#define MT6373_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR		0x1691
#define MT6373_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR		0x1691
#define MT6373_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR		0x1692
#define MT6373_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR		0x1692
#define MT6373_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR		0x1692
#define MT6373_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR		0x1692
#define MT6373_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR		0x1693
#define MT6373_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR		0x1694
#define MT6373_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR		0x1694
#define MT6373_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR		0x1694
#define MT6373_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR		0x1694
#define MT6373_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR		0x1694
#define MT6373_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR		0x1694
#define MT6373_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR		0x1695
#define MT6373_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR		0x1695
#define MT6373_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR		0x1695
#define MT6373_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR		0x1695
#define MT6373_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR		0x1707
#define MT6373_RG_BUCK_VBUCK5_ONLV_EN_ADDR		0x1708
#define MT6373_RG_BUCK_VBUCK5_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR		0x170D
#define MT6373_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR		0x170E
#define MT6373_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR		0x170E
#define MT6373_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR		0x170E
#define MT6373_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR		0x170E
#define MT6373_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR		0x170E
#define MT6373_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR		0x170E
#define MT6373_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR		0x170F
#define MT6373_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR		0x170F
#define MT6373_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR		0x170F
#define MT6373_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR		0x170F
#define MT6373_RG_BUCK_VBUCK5_SW_OP_EN_ADDR		0x170F
#define MT6373_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR		0x1710
#define MT6373_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR		0x1711
#define MT6373_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR		0x1711
#define MT6373_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR		0x1711
#define MT6373_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR		0x1711
#define MT6373_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR		0x1711
#define MT6373_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR		0x1711
#define MT6373_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR		0x1712
#define MT6373_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR		0x1712
#define MT6373_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR		0x1712
#define MT6373_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR		0x1712
#define MT6373_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR		0x1713
#define MT6373_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR		0x1714
#define MT6373_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR		0x1714
#define MT6373_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR		0x1714
#define MT6373_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR		0x1714
#define MT6373_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR		0x1714
#define MT6373_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR		0x1714
#define MT6373_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR		0x1715
#define MT6373_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR		0x1715
#define MT6373_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR		0x1715
#define MT6373_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR		0x1715
#define MT6373_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR		0x1787
#define MT6373_RG_BUCK_VBUCK6_ONLV_EN_ADDR		0x1788
#define MT6373_RG_BUCK_VBUCK6_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR		0x178D
#define MT6373_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR		0x178E
#define MT6373_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR		0x178E
#define MT6373_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR		0x178E
#define MT6373_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR		0x178E
#define MT6373_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR		0x178E
#define MT6373_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR		0x178E
#define MT6373_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR		0x178F
#define MT6373_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR		0x178F
#define MT6373_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR		0x178F
#define MT6373_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR		0x178F
#define MT6373_RG_BUCK_VBUCK6_SW_OP_EN_ADDR		0x178F
#define MT6373_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR		0x1790
#define MT6373_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR		0x1791
#define MT6373_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR		0x1791
#define MT6373_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR		0x1791
#define MT6373_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR		0x1791
#define MT6373_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR		0x1791
#define MT6373_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR		0x1791
#define MT6373_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR		0x1792
#define MT6373_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR		0x1792
#define MT6373_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR		0x1792
#define MT6373_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR		0x1792
#define MT6373_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR		0x1793
#define MT6373_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR		0x1794
#define MT6373_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR		0x1794
#define MT6373_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR		0x1794
#define MT6373_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR		0x1794
#define MT6373_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR		0x1794
#define MT6373_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR		0x1794
#define MT6373_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR		0x1795
#define MT6373_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR		0x1795
#define MT6373_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR		0x1795
#define MT6373_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR		0x1795
#define MT6373_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR		0x1807
#define MT6373_RG_BUCK_VBUCK7_ONLV_EN_ADDR		0x1808
#define MT6373_RG_BUCK_VBUCK7_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR		0x180D
#define MT6373_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR		0x180E
#define MT6373_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR		0x180E
#define MT6373_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR		0x180E
#define MT6373_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR		0x180E
#define MT6373_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR		0x180E
#define MT6373_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR		0x180E
#define MT6373_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR		0x180F
#define MT6373_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR		0x180F
#define MT6373_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR		0x180F
#define MT6373_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR		0x180F
#define MT6373_RG_BUCK_VBUCK7_SW_OP_EN_ADDR		0x180F
#define MT6373_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR		0x1810
#define MT6373_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR		0x1811
#define MT6373_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR		0x1811
#define MT6373_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR		0x1811
#define MT6373_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR		0x1811
#define MT6373_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR		0x1811
#define MT6373_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR		0x1811
#define MT6373_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR		0x1812
#define MT6373_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR		0x1812
#define MT6373_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR		0x1812
#define MT6373_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR		0x1812
#define MT6373_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR		0x1813
#define MT6373_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR		0x1814
#define MT6373_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR		0x1814
#define MT6373_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR		0x1814
#define MT6373_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR		0x1814
#define MT6373_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR		0x1814
#define MT6373_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR		0x1814
#define MT6373_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR		0x1815
#define MT6373_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR		0x1815
#define MT6373_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR		0x1815
#define MT6373_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR		0x1815
#define MT6373_RG_BUCK_VBUCK8_VOSEL_SLEEP_ADDR		0x1887
#define MT6373_RG_BUCK_VBUCK8_ONLV_EN_ADDR		0x1888
#define MT6373_RG_BUCK_VBUCK8_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK8_RC0_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC1_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC2_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC3_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC4_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC5_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC6_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC7_OP_EN_ADDR		0x188D
#define MT6373_RG_BUCK_VBUCK8_RC8_OP_EN_ADDR		0x188E
#define MT6373_RG_BUCK_VBUCK8_RC9_OP_EN_ADDR		0x188E
#define MT6373_RG_BUCK_VBUCK8_RC10_OP_EN_ADDR		0x188E
#define MT6373_RG_BUCK_VBUCK8_RC11_OP_EN_ADDR		0x188E
#define MT6373_RG_BUCK_VBUCK8_RC12_OP_EN_ADDR		0x188E
#define MT6373_RG_BUCK_VBUCK8_RC13_OP_EN_ADDR		0x188E
#define MT6373_RG_BUCK_VBUCK8_HW0_OP_EN_ADDR		0x188F
#define MT6373_RG_BUCK_VBUCK8_HW1_OP_EN_ADDR		0x188F
#define MT6373_RG_BUCK_VBUCK8_HW2_OP_EN_ADDR		0x188F
#define MT6373_RG_BUCK_VBUCK8_HW3_OP_EN_ADDR		0x188F
#define MT6373_RG_BUCK_VBUCK8_SW_OP_EN_ADDR		0x188F
#define MT6373_RG_BUCK_VBUCK8_RC0_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC1_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC2_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC3_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC4_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC5_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC6_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC7_OP_CFG_ADDR		0x1890
#define MT6373_RG_BUCK_VBUCK8_RC8_OP_CFG_ADDR		0x1891
#define MT6373_RG_BUCK_VBUCK8_RC9_OP_CFG_ADDR		0x1891
#define MT6373_RG_BUCK_VBUCK8_RC10_OP_CFG_ADDR		0x1891
#define MT6373_RG_BUCK_VBUCK8_RC11_OP_CFG_ADDR		0x1891
#define MT6373_RG_BUCK_VBUCK8_RC12_OP_CFG_ADDR		0x1891
#define MT6373_RG_BUCK_VBUCK8_RC13_OP_CFG_ADDR		0x1891
#define MT6373_RG_BUCK_VBUCK8_HW0_OP_CFG_ADDR		0x1892
#define MT6373_RG_BUCK_VBUCK8_HW1_OP_CFG_ADDR		0x1892
#define MT6373_RG_BUCK_VBUCK8_HW2_OP_CFG_ADDR		0x1892
#define MT6373_RG_BUCK_VBUCK8_HW3_OP_CFG_ADDR		0x1892
#define MT6373_RG_BUCK_VBUCK8_RC0_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC1_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC2_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC3_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC4_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC5_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC6_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC7_OP_MODE_ADDR		0x1893
#define MT6373_RG_BUCK_VBUCK8_RC8_OP_MODE_ADDR		0x1894
#define MT6373_RG_BUCK_VBUCK8_RC9_OP_MODE_ADDR		0x1894
#define MT6373_RG_BUCK_VBUCK8_RC10_OP_MODE_ADDR		0x1894
#define MT6373_RG_BUCK_VBUCK8_RC11_OP_MODE_ADDR		0x1894
#define MT6373_RG_BUCK_VBUCK8_RC12_OP_MODE_ADDR		0x1894
#define MT6373_RG_BUCK_VBUCK8_RC13_OP_MODE_ADDR		0x1894
#define MT6373_RG_BUCK_VBUCK8_HW0_OP_MODE_ADDR		0x1895
#define MT6373_RG_BUCK_VBUCK8_HW1_OP_MODE_ADDR		0x1895
#define MT6373_RG_BUCK_VBUCK8_HW2_OP_MODE_ADDR		0x1895
#define MT6373_RG_BUCK_VBUCK8_HW3_OP_MODE_ADDR		0x1895
#define MT6373_RG_BUCK_VBUCK9_VOSEL_SLEEP_ADDR		0x1907
#define MT6373_RG_BUCK_VBUCK9_ONLV_EN_ADDR		0x1908
#define MT6373_RG_BUCK_VBUCK9_ONLV_EN_SHIFT		4
#define MT6373_RG_BUCK_VBUCK9_RC0_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC1_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC2_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC3_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC4_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC5_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC6_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC7_OP_EN_ADDR		0x190D
#define MT6373_RG_BUCK_VBUCK9_RC8_OP_EN_ADDR		0x190E
#define MT6373_RG_BUCK_VBUCK9_RC9_OP_EN_ADDR		0x190E
#define MT6373_RG_BUCK_VBUCK9_RC10_OP_EN_ADDR		0x190E
#define MT6373_RG_BUCK_VBUCK9_RC11_OP_EN_ADDR		0x190E
#define MT6373_RG_BUCK_VBUCK9_RC12_OP_EN_ADDR		0x190E
#define MT6373_RG_BUCK_VBUCK9_RC13_OP_EN_ADDR		0x190E
#define MT6373_RG_BUCK_VBUCK9_HW0_OP_EN_ADDR		0x190F
#define MT6373_RG_BUCK_VBUCK9_HW1_OP_EN_ADDR		0x190F
#define MT6373_RG_BUCK_VBUCK9_HW2_OP_EN_ADDR		0x190F
#define MT6373_RG_BUCK_VBUCK9_HW3_OP_EN_ADDR		0x190F
#define MT6373_RG_BUCK_VBUCK9_SW_OP_EN_ADDR		0x190F
#define MT6373_RG_BUCK_VBUCK9_RC0_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC1_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC2_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC3_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC4_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC5_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC6_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC7_OP_CFG_ADDR		0x1910
#define MT6373_RG_BUCK_VBUCK9_RC8_OP_CFG_ADDR		0x1911
#define MT6373_RG_BUCK_VBUCK9_RC9_OP_CFG_ADDR		0x1911
#define MT6373_RG_BUCK_VBUCK9_RC10_OP_CFG_ADDR		0x1911
#define MT6373_RG_BUCK_VBUCK9_RC11_OP_CFG_ADDR		0x1911
#define MT6373_RG_BUCK_VBUCK9_RC12_OP_CFG_ADDR		0x1911
#define MT6373_RG_BUCK_VBUCK9_RC13_OP_CFG_ADDR		0x1911
#define MT6373_RG_BUCK_VBUCK9_HW0_OP_CFG_ADDR		0x1912
#define MT6373_RG_BUCK_VBUCK9_HW1_OP_CFG_ADDR		0x1912
#define MT6373_RG_BUCK_VBUCK9_HW2_OP_CFG_ADDR		0x1912
#define MT6373_RG_BUCK_VBUCK9_HW3_OP_CFG_ADDR		0x1912
#define MT6373_RG_BUCK_VBUCK9_RC0_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC1_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC2_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC3_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC4_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC5_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC6_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC7_OP_MODE_ADDR		0x1913
#define MT6373_RG_BUCK_VBUCK9_RC8_OP_MODE_ADDR		0x1914
#define MT6373_RG_BUCK_VBUCK9_RC9_OP_MODE_ADDR		0x1914
#define MT6373_RG_BUCK_VBUCK9_RC10_OP_MODE_ADDR		0x1914
#define MT6373_RG_BUCK_VBUCK9_RC11_OP_MODE_ADDR		0x1914
#define MT6373_RG_BUCK_VBUCK9_RC12_OP_MODE_ADDR		0x1914
#define MT6373_RG_BUCK_VBUCK9_RC13_OP_MODE_ADDR		0x1914
#define MT6373_RG_BUCK_VBUCK9_HW0_OP_MODE_ADDR		0x1915
#define MT6373_RG_BUCK_VBUCK9_HW1_OP_MODE_ADDR		0x1915
#define MT6373_RG_BUCK_VBUCK9_HW2_OP_MODE_ADDR		0x1915
#define MT6373_RG_BUCK_VBUCK9_HW3_OP_MODE_ADDR		0x1915
#define MT6373_RG_LDO_VAUD18_ONLV_EN_ADDR		0x1B88
#define MT6373_RG_LDO_VAUD18_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VAUD18_RC0_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC1_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC2_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC3_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC4_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC5_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC6_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC7_OP_EN_ADDR		0x1B8C
#define MT6373_RG_LDO_VAUD18_RC8_OP_EN_ADDR		0x1B8D
#define MT6373_RG_LDO_VAUD18_RC9_OP_EN_ADDR		0x1B8D
#define MT6373_RG_LDO_VAUD18_RC10_OP_EN_ADDR		0x1B8D
#define MT6373_RG_LDO_VAUD18_RC11_OP_EN_ADDR		0x1B8D
#define MT6373_RG_LDO_VAUD18_RC12_OP_EN_ADDR		0x1B8D
#define MT6373_RG_LDO_VAUD18_RC13_OP_EN_ADDR		0x1B8D
#define MT6373_RG_LDO_VAUD18_HW0_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_HW1_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_HW2_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_HW3_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_HW4_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_HW5_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_HW6_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_SW_OP_EN_ADDR		0x1B8E
#define MT6373_RG_LDO_VAUD18_RC0_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC1_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC2_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC3_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC4_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC5_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC6_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC7_OP_CFG_ADDR		0x1B8F
#define MT6373_RG_LDO_VAUD18_RC8_OP_CFG_ADDR		0x1B90
#define MT6373_RG_LDO_VAUD18_RC9_OP_CFG_ADDR		0x1B90
#define MT6373_RG_LDO_VAUD18_RC10_OP_CFG_ADDR		0x1B90
#define MT6373_RG_LDO_VAUD18_RC11_OP_CFG_ADDR		0x1B90
#define MT6373_RG_LDO_VAUD18_RC12_OP_CFG_ADDR		0x1B90
#define MT6373_RG_LDO_VAUD18_RC13_OP_CFG_ADDR		0x1B90
#define MT6373_RG_LDO_VAUD18_HW0_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_HW1_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_HW2_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_HW3_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_HW4_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_HW5_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_HW6_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_SW_OP_CFG_ADDR		0x1B91
#define MT6373_RG_LDO_VAUD18_RC0_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC1_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC2_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC3_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC4_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC5_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC6_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC7_OP_MODE_ADDR		0x1B92
#define MT6373_RG_LDO_VAUD18_RC8_OP_MODE_ADDR		0x1B93
#define MT6373_RG_LDO_VAUD18_RC9_OP_MODE_ADDR		0x1B93
#define MT6373_RG_LDO_VAUD18_RC10_OP_MODE_ADDR		0x1B93
#define MT6373_RG_LDO_VAUD18_RC11_OP_MODE_ADDR		0x1B93
#define MT6373_RG_LDO_VAUD18_RC12_OP_MODE_ADDR		0x1B93
#define MT6373_RG_LDO_VAUD18_RC13_OP_MODE_ADDR		0x1B93
#define MT6373_RG_LDO_VAUD18_HW0_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VAUD18_HW1_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VAUD18_HW2_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VAUD18_HW3_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VAUD18_HW4_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VAUD18_HW5_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VAUD18_HW6_OP_MODE_ADDR		0x1B94
#define MT6373_RG_LDO_VUSB_ONLV_EN_ADDR			0x1B96
#define MT6373_RG_LDO_VUSB_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VUSB_RC0_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC1_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC2_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC3_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC4_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC5_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC6_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC7_OP_EN_ADDR		0x1B9A
#define MT6373_RG_LDO_VUSB_RC8_OP_EN_ADDR		0x1B9B
#define MT6373_RG_LDO_VUSB_RC9_OP_EN_ADDR		0x1B9B
#define MT6373_RG_LDO_VUSB_RC10_OP_EN_ADDR		0x1B9B
#define MT6373_RG_LDO_VUSB_RC11_OP_EN_ADDR		0x1B9B
#define MT6373_RG_LDO_VUSB_RC12_OP_EN_ADDR		0x1B9B
#define MT6373_RG_LDO_VUSB_RC13_OP_EN_ADDR		0x1B9B
#define MT6373_RG_LDO_VUSB_HW0_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_HW1_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_HW2_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_HW3_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_HW4_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_HW5_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_HW6_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_SW_OP_EN_ADDR		0x1B9C
#define MT6373_RG_LDO_VUSB_RC0_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC1_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC2_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC3_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC4_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC5_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC6_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC7_OP_CFG_ADDR		0x1B9D
#define MT6373_RG_LDO_VUSB_RC8_OP_CFG_ADDR		0x1B9E
#define MT6373_RG_LDO_VUSB_RC9_OP_CFG_ADDR		0x1B9E
#define MT6373_RG_LDO_VUSB_RC10_OP_CFG_ADDR		0x1B9E
#define MT6373_RG_LDO_VUSB_RC11_OP_CFG_ADDR		0x1B9E
#define MT6373_RG_LDO_VUSB_RC12_OP_CFG_ADDR		0x1B9E
#define MT6373_RG_LDO_VUSB_RC13_OP_CFG_ADDR		0x1B9E
#define MT6373_RG_LDO_VUSB_HW0_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_HW1_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_HW2_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_HW3_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_HW4_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_HW5_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_HW6_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_SW_OP_CFG_ADDR		0x1B9F
#define MT6373_RG_LDO_VUSB_RC0_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC1_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC2_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC3_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC4_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC5_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC6_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC7_OP_MODE_ADDR		0x1BA0
#define MT6373_RG_LDO_VUSB_RC8_OP_MODE_ADDR		0x1BA1
#define MT6373_RG_LDO_VUSB_RC9_OP_MODE_ADDR		0x1BA1
#define MT6373_RG_LDO_VUSB_RC10_OP_MODE_ADDR		0x1BA1
#define MT6373_RG_LDO_VUSB_RC11_OP_MODE_ADDR		0x1BA1
#define MT6373_RG_LDO_VUSB_RC12_OP_MODE_ADDR		0x1BA1
#define MT6373_RG_LDO_VUSB_RC13_OP_MODE_ADDR		0x1BA1
#define MT6373_RG_LDO_VUSB_HW0_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VUSB_HW1_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VUSB_HW2_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VUSB_HW3_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VUSB_HW4_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VUSB_HW5_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VUSB_HW6_OP_MODE_ADDR		0x1BA2
#define MT6373_RG_LDO_VAUX18_ONLV_EN_ADDR		0x1BA4
#define MT6373_RG_LDO_VAUX18_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VAUX18_RC0_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC1_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC2_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC3_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC4_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC5_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC6_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC7_OP_EN_ADDR		0x1BA8
#define MT6373_RG_LDO_VAUX18_RC8_OP_EN_ADDR		0x1BA9
#define MT6373_RG_LDO_VAUX18_RC9_OP_EN_ADDR		0x1BA9
#define MT6373_RG_LDO_VAUX18_RC10_OP_EN_ADDR		0x1BA9
#define MT6373_RG_LDO_VAUX18_RC11_OP_EN_ADDR		0x1BA9
#define MT6373_RG_LDO_VAUX18_RC12_OP_EN_ADDR		0x1BA9
#define MT6373_RG_LDO_VAUX18_RC13_OP_EN_ADDR		0x1BA9
#define MT6373_RG_LDO_VAUX18_HW0_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_HW1_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_HW2_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_HW3_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_HW4_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_HW5_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_HW6_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_SW_OP_EN_ADDR		0x1BAA
#define MT6373_RG_LDO_VAUX18_RC0_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC1_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC2_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC3_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC4_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC5_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC6_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC7_OP_CFG_ADDR		0x1BAB
#define MT6373_RG_LDO_VAUX18_RC8_OP_CFG_ADDR		0x1BAC
#define MT6373_RG_LDO_VAUX18_RC9_OP_CFG_ADDR		0x1BAC
#define MT6373_RG_LDO_VAUX18_RC10_OP_CFG_ADDR		0x1BAC
#define MT6373_RG_LDO_VAUX18_RC11_OP_CFG_ADDR		0x1BAC
#define MT6373_RG_LDO_VAUX18_RC12_OP_CFG_ADDR		0x1BAC
#define MT6373_RG_LDO_VAUX18_RC13_OP_CFG_ADDR		0x1BAC
#define MT6373_RG_LDO_VAUX18_HW0_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_HW1_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_HW2_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_HW3_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_HW4_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_HW5_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_HW6_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_SW_OP_CFG_ADDR		0x1BAD
#define MT6373_RG_LDO_VAUX18_RC0_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC1_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC2_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC3_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC4_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC5_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC6_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC7_OP_MODE_ADDR		0x1BAE
#define MT6373_RG_LDO_VAUX18_RC8_OP_MODE_ADDR		0x1BAF
#define MT6373_RG_LDO_VAUX18_RC9_OP_MODE_ADDR		0x1BAF
#define MT6373_RG_LDO_VAUX18_RC10_OP_MODE_ADDR		0x1BAF
#define MT6373_RG_LDO_VAUX18_RC11_OP_MODE_ADDR		0x1BAF
#define MT6373_RG_LDO_VAUX18_RC12_OP_MODE_ADDR		0x1BAF
#define MT6373_RG_LDO_VAUX18_RC13_OP_MODE_ADDR		0x1BAF
#define MT6373_RG_LDO_VAUX18_HW0_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VAUX18_HW1_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VAUX18_HW2_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VAUX18_HW3_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VAUX18_HW4_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VAUX18_HW5_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VAUX18_HW6_OP_MODE_ADDR		0x1BB0
#define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_ADDR		0x1BB2
#define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_EN_ADDR		0x1BB6
#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_EN_ADDR		0x1BB7
#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_EN_ADDR		0x1BB7
#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_EN_ADDR		0x1BB7
#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_EN_ADDR		0x1BB7
#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_EN_ADDR		0x1BB7
#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_EN_ADDR		0x1BB7
#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_SW_OP_EN_ADDR		0x1BB8
#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_CFG_ADDR		0x1BB9
#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_CFG_ADDR		0x1BBA
#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_CFG_ADDR		0x1BBA
#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_CFG_ADDR	0x1BBA
#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_CFG_ADDR	0x1BBA
#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_CFG_ADDR	0x1BBA
#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_CFG_ADDR	0x1BBA
#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_SW_OP_CFG_ADDR		0x1BBB
#define MT6373_RG_LDO_VRF13_AIF_RC0_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC1_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC2_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC3_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC4_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC5_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC6_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC7_OP_MODE_ADDR	0x1BBC
#define MT6373_RG_LDO_VRF13_AIF_RC8_OP_MODE_ADDR	0x1BBD
#define MT6373_RG_LDO_VRF13_AIF_RC9_OP_MODE_ADDR	0x1BBD
#define MT6373_RG_LDO_VRF13_AIF_RC10_OP_MODE_ADDR	0x1BBD
#define MT6373_RG_LDO_VRF13_AIF_RC11_OP_MODE_ADDR	0x1BBD
#define MT6373_RG_LDO_VRF13_AIF_RC12_OP_MODE_ADDR	0x1BBD
#define MT6373_RG_LDO_VRF13_AIF_RC13_OP_MODE_ADDR	0x1BBD
#define MT6373_RG_LDO_VRF13_AIF_HW0_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF13_AIF_HW1_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF13_AIF_HW2_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF13_AIF_HW3_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF13_AIF_HW4_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF13_AIF_HW5_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF13_AIF_HW6_OP_MODE_ADDR	0x1BBE
#define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_ADDR		0x1BC0
#define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_EN_ADDR		0x1BC4
#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_EN_ADDR		0x1BC5
#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_EN_ADDR		0x1BC5
#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_EN_ADDR		0x1BC5
#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_EN_ADDR		0x1BC5
#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_EN_ADDR		0x1BC5
#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_EN_ADDR		0x1BC5
#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_SW_OP_EN_ADDR		0x1BC6
#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_CFG_ADDR		0x1BC7
#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_CFG_ADDR		0x1BC8
#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_CFG_ADDR		0x1BC8
#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_CFG_ADDR	0x1BC8
#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_CFG_ADDR	0x1BC8
#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_CFG_ADDR	0x1BC8
#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_CFG_ADDR	0x1BC8
#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_SW_OP_CFG_ADDR		0x1BC9
#define MT6373_RG_LDO_VRF18_AIF_RC0_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC1_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC2_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC3_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC4_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC5_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC6_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC7_OP_MODE_ADDR	0x1BCA
#define MT6373_RG_LDO_VRF18_AIF_RC8_OP_MODE_ADDR	0x1BCB
#define MT6373_RG_LDO_VRF18_AIF_RC9_OP_MODE_ADDR	0x1BCB
#define MT6373_RG_LDO_VRF18_AIF_RC10_OP_MODE_ADDR	0x1BCB
#define MT6373_RG_LDO_VRF18_AIF_RC11_OP_MODE_ADDR	0x1BCB
#define MT6373_RG_LDO_VRF18_AIF_RC12_OP_MODE_ADDR	0x1BCB
#define MT6373_RG_LDO_VRF18_AIF_RC13_OP_MODE_ADDR	0x1BCB
#define MT6373_RG_LDO_VRF18_AIF_HW0_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRF18_AIF_HW1_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRF18_AIF_HW2_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRF18_AIF_HW3_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRF18_AIF_HW4_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRF18_AIF_HW5_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRF18_AIF_HW6_OP_MODE_ADDR	0x1BCC
#define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_ADDR		0x1BCE
#define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_EN_ADDR	0x1BD2
#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_EN_ADDR	0x1BD3
#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_EN_ADDR	0x1BD3
#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_EN_ADDR	0x1BD3
#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_EN_ADDR	0x1BD3
#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_EN_ADDR	0x1BD3
#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_EN_ADDR	0x1BD3
#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_EN_ADDR	0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_EN_ADDR		0x1BD4
#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_CFG_ADDR	0x1BD5
#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_CFG_ADDR	0x1BD6
#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_CFG_ADDR	0x1BD6
#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_CFG_ADDR	0x1BD6
#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_CFG_ADDR	0x1BD6
#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_CFG_ADDR	0x1BD6
#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_CFG_ADDR	0x1BD6
#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_CFG_ADDR	0x1BD7
#define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_MODE_ADDR	0x1BD8
#define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_MODE_ADDR	0x1BD9
#define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_MODE_ADDR	0x1BD9
#define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_MODE_ADDR	0x1BD9
#define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_MODE_ADDR	0x1BD9
#define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_MODE_ADDR	0x1BD9
#define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_MODE_ADDR	0x1BD9
#define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_MODE_ADDR	0x1BDA
#define MT6373_RG_LDO_VCN33_1_ONLV_EN_ADDR		0x1C08
#define MT6373_RG_LDO_VCN33_1_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VCN33_1_RC0_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC1_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC2_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC3_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC4_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC5_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC6_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC7_OP_EN_ADDR		0x1C0C
#define MT6373_RG_LDO_VCN33_1_RC8_OP_EN_ADDR		0x1C0D
#define MT6373_RG_LDO_VCN33_1_RC9_OP_EN_ADDR		0x1C0D
#define MT6373_RG_LDO_VCN33_1_RC10_OP_EN_ADDR		0x1C0D
#define MT6373_RG_LDO_VCN33_1_RC11_OP_EN_ADDR		0x1C0D
#define MT6373_RG_LDO_VCN33_1_RC12_OP_EN_ADDR		0x1C0D
#define MT6373_RG_LDO_VCN33_1_RC13_OP_EN_ADDR		0x1C0D
#define MT6373_RG_LDO_VCN33_1_HW0_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_HW1_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_HW2_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_HW3_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_HW4_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_HW5_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_HW6_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_SW_OP_EN_ADDR		0x1C0E
#define MT6373_RG_LDO_VCN33_1_RC0_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC1_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC2_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC3_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC4_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC5_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC6_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC7_OP_CFG_ADDR		0x1C0F
#define MT6373_RG_LDO_VCN33_1_RC8_OP_CFG_ADDR		0x1C10
#define MT6373_RG_LDO_VCN33_1_RC9_OP_CFG_ADDR		0x1C10
#define MT6373_RG_LDO_VCN33_1_RC10_OP_CFG_ADDR		0x1C10
#define MT6373_RG_LDO_VCN33_1_RC11_OP_CFG_ADDR		0x1C10
#define MT6373_RG_LDO_VCN33_1_RC12_OP_CFG_ADDR		0x1C10
#define MT6373_RG_LDO_VCN33_1_RC13_OP_CFG_ADDR		0x1C10
#define MT6373_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_SW_OP_CFG_ADDR		0x1C11
#define MT6373_RG_LDO_VCN33_1_RC0_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC1_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC2_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC3_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC4_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC5_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC6_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC7_OP_MODE_ADDR		0x1C12
#define MT6373_RG_LDO_VCN33_1_RC8_OP_MODE_ADDR		0x1C13
#define MT6373_RG_LDO_VCN33_1_RC9_OP_MODE_ADDR		0x1C13
#define MT6373_RG_LDO_VCN33_1_RC10_OP_MODE_ADDR		0x1C13
#define MT6373_RG_LDO_VCN33_1_RC11_OP_MODE_ADDR		0x1C13
#define MT6373_RG_LDO_VCN33_1_RC12_OP_MODE_ADDR		0x1C13
#define MT6373_RG_LDO_VCN33_1_RC13_OP_MODE_ADDR		0x1C13
#define MT6373_RG_LDO_VCN33_1_HW0_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_1_HW1_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_1_HW2_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_1_HW3_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_1_HW4_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_1_HW5_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_1_HW6_OP_MODE_ADDR		0x1C14
#define MT6373_RG_LDO_VCN33_2_ONLV_EN_ADDR		0x1C16
#define MT6373_RG_LDO_VCN33_2_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VCN33_2_RC0_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC1_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC2_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC3_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC4_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC5_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC6_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC7_OP_EN_ADDR		0x1C1A
#define MT6373_RG_LDO_VCN33_2_RC8_OP_EN_ADDR		0x1C1B
#define MT6373_RG_LDO_VCN33_2_RC9_OP_EN_ADDR		0x1C1B
#define MT6373_RG_LDO_VCN33_2_RC10_OP_EN_ADDR		0x1C1B
#define MT6373_RG_LDO_VCN33_2_RC11_OP_EN_ADDR		0x1C1B
#define MT6373_RG_LDO_VCN33_2_RC12_OP_EN_ADDR		0x1C1B
#define MT6373_RG_LDO_VCN33_2_RC13_OP_EN_ADDR		0x1C1B
#define MT6373_RG_LDO_VCN33_2_HW0_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_HW1_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_HW2_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_HW3_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_HW4_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_HW5_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_HW6_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_SW_OP_EN_ADDR		0x1C1C
#define MT6373_RG_LDO_VCN33_2_RC0_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC1_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC2_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC3_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC4_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC5_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC6_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC7_OP_CFG_ADDR		0x1C1D
#define MT6373_RG_LDO_VCN33_2_RC8_OP_CFG_ADDR		0x1C1E
#define MT6373_RG_LDO_VCN33_2_RC9_OP_CFG_ADDR		0x1C1E
#define MT6373_RG_LDO_VCN33_2_RC10_OP_CFG_ADDR		0x1C1E
#define MT6373_RG_LDO_VCN33_2_RC11_OP_CFG_ADDR		0x1C1E
#define MT6373_RG_LDO_VCN33_2_RC12_OP_CFG_ADDR		0x1C1E
#define MT6373_RG_LDO_VCN33_2_RC13_OP_CFG_ADDR		0x1C1E
#define MT6373_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_SW_OP_CFG_ADDR		0x1C1F
#define MT6373_RG_LDO_VCN33_2_RC0_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC1_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC2_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC3_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC4_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC5_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC6_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC7_OP_MODE_ADDR		0x1C20
#define MT6373_RG_LDO_VCN33_2_RC8_OP_MODE_ADDR		0x1C21
#define MT6373_RG_LDO_VCN33_2_RC9_OP_MODE_ADDR		0x1C21
#define MT6373_RG_LDO_VCN33_2_RC10_OP_MODE_ADDR		0x1C21
#define MT6373_RG_LDO_VCN33_2_RC11_OP_MODE_ADDR		0x1C21
#define MT6373_RG_LDO_VCN33_2_RC12_OP_MODE_ADDR		0x1C21
#define MT6373_RG_LDO_VCN33_2_RC13_OP_MODE_ADDR		0x1C21
#define MT6373_RG_LDO_VCN33_2_HW0_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_2_HW1_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_2_HW2_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_2_HW3_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_2_HW4_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_2_HW5_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_2_HW6_OP_MODE_ADDR		0x1C22
#define MT6373_RG_LDO_VCN33_3_ONLV_EN_ADDR		0x1C24
#define MT6373_RG_LDO_VCN33_3_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VCN33_3_RC0_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC1_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC2_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC3_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC4_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC5_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC6_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC7_OP_EN_ADDR		0x1C28
#define MT6373_RG_LDO_VCN33_3_RC8_OP_EN_ADDR		0x1C29
#define MT6373_RG_LDO_VCN33_3_RC9_OP_EN_ADDR		0x1C29
#define MT6373_RG_LDO_VCN33_3_RC10_OP_EN_ADDR		0x1C29
#define MT6373_RG_LDO_VCN33_3_RC11_OP_EN_ADDR		0x1C29
#define MT6373_RG_LDO_VCN33_3_RC12_OP_EN_ADDR		0x1C29
#define MT6373_RG_LDO_VCN33_3_RC13_OP_EN_ADDR		0x1C29
#define MT6373_RG_LDO_VCN33_3_HW0_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_HW1_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_HW2_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_HW3_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_HW4_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_HW5_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_HW6_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_SW_OP_EN_ADDR		0x1C2A
#define MT6373_RG_LDO_VCN33_3_RC0_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC1_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC2_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC3_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC4_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC5_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC6_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC7_OP_CFG_ADDR		0x1C2B
#define MT6373_RG_LDO_VCN33_3_RC8_OP_CFG_ADDR		0x1C2C
#define MT6373_RG_LDO_VCN33_3_RC9_OP_CFG_ADDR		0x1C2C
#define MT6373_RG_LDO_VCN33_3_RC10_OP_CFG_ADDR		0x1C2C
#define MT6373_RG_LDO_VCN33_3_RC11_OP_CFG_ADDR		0x1C2C
#define MT6373_RG_LDO_VCN33_3_RC12_OP_CFG_ADDR		0x1C2C
#define MT6373_RG_LDO_VCN33_3_RC13_OP_CFG_ADDR		0x1C2C
#define MT6373_RG_LDO_VCN33_3_HW0_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_HW1_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_HW2_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_HW3_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_HW4_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_HW5_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_HW6_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_SW_OP_CFG_ADDR		0x1C2D
#define MT6373_RG_LDO_VCN33_3_RC0_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC1_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC2_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC3_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC4_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC5_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC6_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC7_OP_MODE_ADDR		0x1C2E
#define MT6373_RG_LDO_VCN33_3_RC8_OP_MODE_ADDR		0x1C2F
#define MT6373_RG_LDO_VCN33_3_RC9_OP_MODE_ADDR		0x1C2F
#define MT6373_RG_LDO_VCN33_3_RC10_OP_MODE_ADDR		0x1C2F
#define MT6373_RG_LDO_VCN33_3_RC11_OP_MODE_ADDR		0x1C2F
#define MT6373_RG_LDO_VCN33_3_RC12_OP_MODE_ADDR		0x1C2F
#define MT6373_RG_LDO_VCN33_3_RC13_OP_MODE_ADDR		0x1C2F
#define MT6373_RG_LDO_VCN33_3_HW0_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN33_3_HW1_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN33_3_HW2_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN33_3_HW3_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN33_3_HW4_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN33_3_HW5_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN33_3_HW6_OP_MODE_ADDR		0x1C30
#define MT6373_RG_LDO_VCN18IO_ONLV_EN_ADDR		0x1C32
#define MT6373_RG_LDO_VCN18IO_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VCN18IO_RC0_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC1_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC2_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC3_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC4_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC5_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC6_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC7_OP_EN_ADDR		0x1C36
#define MT6373_RG_LDO_VCN18IO_RC8_OP_EN_ADDR		0x1C37
#define MT6373_RG_LDO_VCN18IO_RC9_OP_EN_ADDR		0x1C37
#define MT6373_RG_LDO_VCN18IO_RC10_OP_EN_ADDR		0x1C37
#define MT6373_RG_LDO_VCN18IO_RC11_OP_EN_ADDR		0x1C37
#define MT6373_RG_LDO_VCN18IO_RC12_OP_EN_ADDR		0x1C37
#define MT6373_RG_LDO_VCN18IO_RC13_OP_EN_ADDR		0x1C37
#define MT6373_RG_LDO_VCN18IO_HW0_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_HW1_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_HW2_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_HW3_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_HW4_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_HW5_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_HW6_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_SW_OP_EN_ADDR		0x1C38
#define MT6373_RG_LDO_VCN18IO_RC0_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC1_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC2_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC3_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC4_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC5_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC6_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC7_OP_CFG_ADDR		0x1C39
#define MT6373_RG_LDO_VCN18IO_RC8_OP_CFG_ADDR		0x1C3A
#define MT6373_RG_LDO_VCN18IO_RC9_OP_CFG_ADDR		0x1C3A
#define MT6373_RG_LDO_VCN18IO_RC10_OP_CFG_ADDR		0x1C3A
#define MT6373_RG_LDO_VCN18IO_RC11_OP_CFG_ADDR		0x1C3A
#define MT6373_RG_LDO_VCN18IO_RC12_OP_CFG_ADDR		0x1C3A
#define MT6373_RG_LDO_VCN18IO_RC13_OP_CFG_ADDR		0x1C3A
#define MT6373_RG_LDO_VCN18IO_HW0_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_HW1_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_HW2_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_HW3_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_HW4_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_HW5_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_HW6_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_SW_OP_CFG_ADDR		0x1C3B
#define MT6373_RG_LDO_VCN18IO_RC0_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC1_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC2_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC3_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC4_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC5_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC6_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC7_OP_MODE_ADDR		0x1C3C
#define MT6373_RG_LDO_VCN18IO_RC8_OP_MODE_ADDR		0x1C3D
#define MT6373_RG_LDO_VCN18IO_RC9_OP_MODE_ADDR		0x1C3D
#define MT6373_RG_LDO_VCN18IO_RC10_OP_MODE_ADDR		0x1C3D
#define MT6373_RG_LDO_VCN18IO_RC11_OP_MODE_ADDR		0x1C3D
#define MT6373_RG_LDO_VCN18IO_RC12_OP_MODE_ADDR		0x1C3D
#define MT6373_RG_LDO_VCN18IO_RC13_OP_MODE_ADDR		0x1C3D
#define MT6373_RG_LDO_VCN18IO_HW0_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VCN18IO_HW1_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VCN18IO_HW2_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VCN18IO_HW3_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VCN18IO_HW4_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VCN18IO_HW5_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VCN18IO_HW6_OP_MODE_ADDR		0x1C3E
#define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_ADDR		0x1C40
#define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_EN_ADDR		0x1C44
#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_EN_ADDR		0x1C45
#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_EN_ADDR		0x1C45
#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_EN_ADDR		0x1C45
#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_EN_ADDR		0x1C45
#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_EN_ADDR		0x1C45
#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_EN_ADDR		0x1C45
#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_SW_OP_EN_ADDR		0x1C46
#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_CFG_ADDR		0x1C47
#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_CFG_ADDR		0x1C48
#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_CFG_ADDR		0x1C48
#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_CFG_ADDR	0x1C48
#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_CFG_ADDR	0x1C48
#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_CFG_ADDR	0x1C48
#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_CFG_ADDR	0x1C48
#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_SW_OP_CFG_ADDR		0x1C49
#define MT6373_RG_LDO_VRF09_AIF_RC0_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC1_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC2_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC3_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC4_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC5_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC6_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC7_OP_MODE_ADDR	0x1C4A
#define MT6373_RG_LDO_VRF09_AIF_RC8_OP_MODE_ADDR	0x1C4B
#define MT6373_RG_LDO_VRF09_AIF_RC9_OP_MODE_ADDR	0x1C4B
#define MT6373_RG_LDO_VRF09_AIF_RC10_OP_MODE_ADDR	0x1C4B
#define MT6373_RG_LDO_VRF09_AIF_RC11_OP_MODE_ADDR	0x1C4B
#define MT6373_RG_LDO_VRF09_AIF_RC12_OP_MODE_ADDR	0x1C4B
#define MT6373_RG_LDO_VRF09_AIF_RC13_OP_MODE_ADDR	0x1C4B
#define MT6373_RG_LDO_VRF09_AIF_HW0_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF09_AIF_HW1_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF09_AIF_HW2_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF09_AIF_HW3_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF09_AIF_HW4_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF09_AIF_HW5_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF09_AIF_HW6_OP_MODE_ADDR	0x1C4C
#define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_ADDR		0x1C4E
#define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_EN_ADDR		0x1C52
#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_EN_ADDR		0x1C53
#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_EN_ADDR		0x1C53
#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_EN_ADDR		0x1C53
#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_EN_ADDR		0x1C53
#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_EN_ADDR		0x1C53
#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_EN_ADDR		0x1C53
#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_SW_OP_EN_ADDR		0x1C54
#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_CFG_ADDR		0x1C55
#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_CFG_ADDR		0x1C56
#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_CFG_ADDR		0x1C56
#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_CFG_ADDR	0x1C56
#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_CFG_ADDR	0x1C56
#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_CFG_ADDR	0x1C56
#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_CFG_ADDR	0x1C56
#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_SW_OP_CFG_ADDR		0x1C57
#define MT6373_RG_LDO_VRF12_AIF_RC0_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC1_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC2_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC3_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC4_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC5_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC6_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC7_OP_MODE_ADDR	0x1C58
#define MT6373_RG_LDO_VRF12_AIF_RC8_OP_MODE_ADDR	0x1C59
#define MT6373_RG_LDO_VRF12_AIF_RC9_OP_MODE_ADDR	0x1C59
#define MT6373_RG_LDO_VRF12_AIF_RC10_OP_MODE_ADDR	0x1C59
#define MT6373_RG_LDO_VRF12_AIF_RC11_OP_MODE_ADDR	0x1C59
#define MT6373_RG_LDO_VRF12_AIF_RC12_OP_MODE_ADDR	0x1C59
#define MT6373_RG_LDO_VRF12_AIF_RC13_OP_MODE_ADDR	0x1C59
#define MT6373_RG_LDO_VRF12_AIF_HW0_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VRF12_AIF_HW1_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VRF12_AIF_HW2_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VRF12_AIF_HW3_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VRF12_AIF_HW4_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VRF12_AIF_HW5_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VRF12_AIF_HW6_OP_MODE_ADDR	0x1C5A
#define MT6373_RG_LDO_VANT18_ONLV_EN_ADDR		0x1C88
#define MT6373_RG_LDO_VANT18_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VANT18_RC0_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC1_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC2_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC3_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC4_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC5_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC6_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC7_OP_EN_ADDR		0x1C8C
#define MT6373_RG_LDO_VANT18_RC8_OP_EN_ADDR		0x1C8D
#define MT6373_RG_LDO_VANT18_RC9_OP_EN_ADDR		0x1C8D
#define MT6373_RG_LDO_VANT18_RC10_OP_EN_ADDR		0x1C8D
#define MT6373_RG_LDO_VANT18_RC11_OP_EN_ADDR		0x1C8D
#define MT6373_RG_LDO_VANT18_RC12_OP_EN_ADDR		0x1C8D
#define MT6373_RG_LDO_VANT18_RC13_OP_EN_ADDR		0x1C8D
#define MT6373_RG_LDO_VANT18_HW0_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_HW1_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_HW2_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_HW3_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_HW4_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_HW5_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_HW6_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_SW_OP_EN_ADDR		0x1C8E
#define MT6373_RG_LDO_VANT18_RC0_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC1_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC2_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC3_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC4_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC5_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC6_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC7_OP_CFG_ADDR		0x1C8F
#define MT6373_RG_LDO_VANT18_RC8_OP_CFG_ADDR		0x1C90
#define MT6373_RG_LDO_VANT18_RC9_OP_CFG_ADDR		0x1C90
#define MT6373_RG_LDO_VANT18_RC10_OP_CFG_ADDR		0x1C90
#define MT6373_RG_LDO_VANT18_RC11_OP_CFG_ADDR		0x1C90
#define MT6373_RG_LDO_VANT18_RC12_OP_CFG_ADDR		0x1C90
#define MT6373_RG_LDO_VANT18_RC13_OP_CFG_ADDR		0x1C90
#define MT6373_RG_LDO_VANT18_HW0_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_HW1_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_HW2_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_HW3_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_HW4_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_HW5_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_HW6_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_SW_OP_CFG_ADDR		0x1C91
#define MT6373_RG_LDO_VANT18_RC0_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC1_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC2_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC3_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC4_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC5_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC6_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC7_OP_MODE_ADDR		0x1C92
#define MT6373_RG_LDO_VANT18_RC8_OP_MODE_ADDR		0x1C93
#define MT6373_RG_LDO_VANT18_RC9_OP_MODE_ADDR		0x1C93
#define MT6373_RG_LDO_VANT18_RC10_OP_MODE_ADDR		0x1C93
#define MT6373_RG_LDO_VANT18_RC11_OP_MODE_ADDR		0x1C93
#define MT6373_RG_LDO_VANT18_RC12_OP_MODE_ADDR		0x1C93
#define MT6373_RG_LDO_VANT18_RC13_OP_MODE_ADDR		0x1C93
#define MT6373_RG_LDO_VANT18_HW0_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VANT18_HW1_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VANT18_HW2_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VANT18_HW3_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VANT18_HW4_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VANT18_HW5_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VANT18_HW6_OP_MODE_ADDR		0x1C94
#define MT6373_RG_LDO_VMDDR_ONLV_EN_ADDR		0x1C96
#define MT6373_RG_LDO_VMDDR_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VMDDR_RC0_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC1_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC2_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC3_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC4_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC5_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC6_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC7_OP_EN_ADDR		0x1C9A
#define MT6373_RG_LDO_VMDDR_RC8_OP_EN_ADDR		0x1C9B
#define MT6373_RG_LDO_VMDDR_RC9_OP_EN_ADDR		0x1C9B
#define MT6373_RG_LDO_VMDDR_RC10_OP_EN_ADDR		0x1C9B
#define MT6373_RG_LDO_VMDDR_RC11_OP_EN_ADDR		0x1C9B
#define MT6373_RG_LDO_VMDDR_RC12_OP_EN_ADDR		0x1C9B
#define MT6373_RG_LDO_VMDDR_RC13_OP_EN_ADDR		0x1C9B
#define MT6373_RG_LDO_VMDDR_HW0_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_HW1_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_HW2_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_HW3_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_HW4_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_HW5_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_HW6_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_SW_OP_EN_ADDR		0x1C9C
#define MT6373_RG_LDO_VMDDR_RC0_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC1_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC2_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC3_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC4_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC5_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC6_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC7_OP_CFG_ADDR		0x1C9D
#define MT6373_RG_LDO_VMDDR_RC8_OP_CFG_ADDR		0x1C9E
#define MT6373_RG_LDO_VMDDR_RC9_OP_CFG_ADDR		0x1C9E
#define MT6373_RG_LDO_VMDDR_RC10_OP_CFG_ADDR		0x1C9E
#define MT6373_RG_LDO_VMDDR_RC11_OP_CFG_ADDR		0x1C9E
#define MT6373_RG_LDO_VMDDR_RC12_OP_CFG_ADDR		0x1C9E
#define MT6373_RG_LDO_VMDDR_RC13_OP_CFG_ADDR		0x1C9E
#define MT6373_RG_LDO_VMDDR_HW0_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_HW1_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_HW2_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_HW3_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_HW4_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_HW5_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_HW6_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_SW_OP_CFG_ADDR		0x1C9F
#define MT6373_RG_LDO_VMDDR_RC0_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC1_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC2_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC3_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC4_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC5_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC6_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC7_OP_MODE_ADDR		0x1CA0
#define MT6373_RG_LDO_VMDDR_RC8_OP_MODE_ADDR		0x1CA1
#define MT6373_RG_LDO_VMDDR_RC9_OP_MODE_ADDR		0x1CA1
#define MT6373_RG_LDO_VMDDR_RC10_OP_MODE_ADDR		0x1CA1
#define MT6373_RG_LDO_VMDDR_RC11_OP_MODE_ADDR		0x1CA1
#define MT6373_RG_LDO_VMDDR_RC12_OP_MODE_ADDR		0x1CA1
#define MT6373_RG_LDO_VMDDR_RC13_OP_MODE_ADDR		0x1CA1
#define MT6373_RG_LDO_VMDDR_HW0_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VMDDR_HW1_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VMDDR_HW2_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VMDDR_HW3_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VMDDR_HW4_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VMDDR_HW5_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VMDDR_HW6_OP_MODE_ADDR		0x1CA2
#define MT6373_RG_LDO_VEFUSE_ONLV_EN_ADDR		0x1CA4
#define MT6373_RG_LDO_VEFUSE_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VEFUSE_RC0_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC1_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC2_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC3_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC4_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC5_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC6_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC7_OP_EN_ADDR		0x1CA8
#define MT6373_RG_LDO_VEFUSE_RC8_OP_EN_ADDR		0x1CA9
#define MT6373_RG_LDO_VEFUSE_RC9_OP_EN_ADDR		0x1CA9
#define MT6373_RG_LDO_VEFUSE_RC10_OP_EN_ADDR		0x1CA9
#define MT6373_RG_LDO_VEFUSE_RC11_OP_EN_ADDR		0x1CA9
#define MT6373_RG_LDO_VEFUSE_RC12_OP_EN_ADDR		0x1CA9
#define MT6373_RG_LDO_VEFUSE_RC13_OP_EN_ADDR		0x1CA9
#define MT6373_RG_LDO_VEFUSE_HW0_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_HW1_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_HW2_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_HW3_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_HW4_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_HW5_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_HW6_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_SW_OP_EN_ADDR		0x1CAA
#define MT6373_RG_LDO_VEFUSE_RC0_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC1_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC2_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC3_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC4_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC5_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC6_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC7_OP_CFG_ADDR		0x1CAB
#define MT6373_RG_LDO_VEFUSE_RC8_OP_CFG_ADDR		0x1CAC
#define MT6373_RG_LDO_VEFUSE_RC9_OP_CFG_ADDR		0x1CAC
#define MT6373_RG_LDO_VEFUSE_RC10_OP_CFG_ADDR		0x1CAC
#define MT6373_RG_LDO_VEFUSE_RC11_OP_CFG_ADDR		0x1CAC
#define MT6373_RG_LDO_VEFUSE_RC12_OP_CFG_ADDR		0x1CAC
#define MT6373_RG_LDO_VEFUSE_RC13_OP_CFG_ADDR		0x1CAC
#define MT6373_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_SW_OP_CFG_ADDR		0x1CAD
#define MT6373_RG_LDO_VEFUSE_RC0_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC1_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC2_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC3_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC4_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC5_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC6_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC7_OP_MODE_ADDR		0x1CAE
#define MT6373_RG_LDO_VEFUSE_RC8_OP_MODE_ADDR		0x1CAF
#define MT6373_RG_LDO_VEFUSE_RC9_OP_MODE_ADDR		0x1CAF
#define MT6373_RG_LDO_VEFUSE_RC10_OP_MODE_ADDR		0x1CAF
#define MT6373_RG_LDO_VEFUSE_RC11_OP_MODE_ADDR		0x1CAF
#define MT6373_RG_LDO_VEFUSE_RC12_OP_MODE_ADDR		0x1CAF
#define MT6373_RG_LDO_VEFUSE_RC13_OP_MODE_ADDR		0x1CAF
#define MT6373_RG_LDO_VEFUSE_HW0_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VEFUSE_HW1_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VEFUSE_HW2_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VEFUSE_HW3_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VEFUSE_HW4_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VEFUSE_HW5_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VEFUSE_HW6_OP_MODE_ADDR		0x1CB0
#define MT6373_RG_LDO_VMCH_ONLV_EN_ADDR			0x1CB2
#define MT6373_RG_LDO_VMCH_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VMCH_RC0_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC1_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC2_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC3_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC4_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC5_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC6_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC7_OP_EN_ADDR		0x1CB6
#define MT6373_RG_LDO_VMCH_RC8_OP_EN_ADDR		0x1CB7
#define MT6373_RG_LDO_VMCH_RC9_OP_EN_ADDR		0x1CB7
#define MT6373_RG_LDO_VMCH_RC10_OP_EN_ADDR		0x1CB7
#define MT6373_RG_LDO_VMCH_RC11_OP_EN_ADDR		0x1CB7
#define MT6373_RG_LDO_VMCH_RC12_OP_EN_ADDR		0x1CB7
#define MT6373_RG_LDO_VMCH_RC13_OP_EN_ADDR		0x1CB7
#define MT6373_RG_LDO_VMCH_HW0_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_HW1_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_HW2_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_HW3_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_HW4_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_HW5_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_HW6_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_SW_OP_EN_ADDR		0x1CB8
#define MT6373_RG_LDO_VMCH_RC0_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC1_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC2_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC3_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC4_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC5_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC6_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC7_OP_CFG_ADDR		0x1CB9
#define MT6373_RG_LDO_VMCH_RC8_OP_CFG_ADDR		0x1CBA
#define MT6373_RG_LDO_VMCH_RC9_OP_CFG_ADDR		0x1CBA
#define MT6373_RG_LDO_VMCH_RC10_OP_CFG_ADDR		0x1CBA
#define MT6373_RG_LDO_VMCH_RC11_OP_CFG_ADDR		0x1CBA
#define MT6373_RG_LDO_VMCH_RC12_OP_CFG_ADDR		0x1CBA
#define MT6373_RG_LDO_VMCH_RC13_OP_CFG_ADDR		0x1CBA
#define MT6373_RG_LDO_VMCH_HW0_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_HW1_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_HW2_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_HW3_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_HW4_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_HW5_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_HW6_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_SW_OP_CFG_ADDR		0x1CBB
#define MT6373_RG_LDO_VMCH_RC0_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC1_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC2_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC3_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC4_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC5_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC6_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC7_OP_MODE_ADDR		0x1CBC
#define MT6373_RG_LDO_VMCH_RC8_OP_MODE_ADDR		0x1CBD
#define MT6373_RG_LDO_VMCH_RC9_OP_MODE_ADDR		0x1CBD
#define MT6373_RG_LDO_VMCH_RC10_OP_MODE_ADDR		0x1CBD
#define MT6373_RG_LDO_VMCH_RC11_OP_MODE_ADDR		0x1CBD
#define MT6373_RG_LDO_VMCH_RC12_OP_MODE_ADDR		0x1CBD
#define MT6373_RG_LDO_VMCH_RC13_OP_MODE_ADDR		0x1CBD
#define MT6373_RG_LDO_VMCH_HW0_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMCH_HW1_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMCH_HW2_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMCH_HW3_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMCH_HW4_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMCH_HW5_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMCH_HW6_OP_MODE_ADDR		0x1CBE
#define MT6373_RG_LDO_VMC_ONLV_EN_ADDR			0x1CC1
#define MT6373_RG_LDO_VMC_ONLV_EN_SHIFT			3
#define MT6373_RG_LDO_VMC_RC0_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC1_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC2_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC3_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC4_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC5_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC6_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC7_OP_EN_ADDR		0x1CC5
#define MT6373_RG_LDO_VMC_RC8_OP_EN_ADDR		0x1CC6
#define MT6373_RG_LDO_VMC_RC9_OP_EN_ADDR		0x1CC6
#define MT6373_RG_LDO_VMC_RC10_OP_EN_ADDR		0x1CC6
#define MT6373_RG_LDO_VMC_RC11_OP_EN_ADDR		0x1CC6
#define MT6373_RG_LDO_VMC_RC12_OP_EN_ADDR		0x1CC6
#define MT6373_RG_LDO_VMC_RC13_OP_EN_ADDR		0x1CC6
#define MT6373_RG_LDO_VMC_HW0_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_HW1_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_HW2_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_HW3_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_HW4_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_HW5_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_HW6_OP_EN_ADDR		0x1CC7
#define MT6373_RG_LDO_VMC_SW_OP_EN_ADDR			0x1CC7
#define MT6373_RG_LDO_VMC_RC0_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC1_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC2_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC3_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC4_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC5_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC6_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC7_OP_CFG_ADDR		0x1CC8
#define MT6373_RG_LDO_VMC_RC8_OP_CFG_ADDR		0x1CC9
#define MT6373_RG_LDO_VMC_RC9_OP_CFG_ADDR		0x1CC9
#define MT6373_RG_LDO_VMC_RC10_OP_CFG_ADDR		0x1CC9
#define MT6373_RG_LDO_VMC_RC11_OP_CFG_ADDR		0x1CC9
#define MT6373_RG_LDO_VMC_RC12_OP_CFG_ADDR		0x1CC9
#define MT6373_RG_LDO_VMC_RC13_OP_CFG_ADDR		0x1CC9
#define MT6373_RG_LDO_VMC_HW0_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_HW1_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_HW2_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_HW3_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_HW4_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_HW5_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_HW6_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_SW_OP_CFG_ADDR		0x1CCA
#define MT6373_RG_LDO_VMC_RC0_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC1_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC2_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC3_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC4_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC5_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC6_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC7_OP_MODE_ADDR		0x1CCB
#define MT6373_RG_LDO_VMC_RC8_OP_MODE_ADDR		0x1CCC
#define MT6373_RG_LDO_VMC_RC9_OP_MODE_ADDR		0x1CCC
#define MT6373_RG_LDO_VMC_RC10_OP_MODE_ADDR		0x1CCC
#define MT6373_RG_LDO_VMC_RC11_OP_MODE_ADDR		0x1CCC
#define MT6373_RG_LDO_VMC_RC12_OP_MODE_ADDR		0x1CCC
#define MT6373_RG_LDO_VMC_RC13_OP_MODE_ADDR		0x1CCC
#define MT6373_RG_LDO_VMC_HW0_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VMC_HW1_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VMC_HW2_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VMC_HW3_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VMC_HW4_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VMC_HW5_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VMC_HW6_OP_MODE_ADDR		0x1CCD
#define MT6373_RG_LDO_VIBR_ONLV_EN_ADDR			0x1CCF
#define MT6373_RG_LDO_VIBR_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VIBR_RC0_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC1_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC2_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC3_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC4_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC5_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC6_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC7_OP_EN_ADDR		0x1CD3
#define MT6373_RG_LDO_VIBR_RC8_OP_EN_ADDR		0x1CD4
#define MT6373_RG_LDO_VIBR_RC9_OP_EN_ADDR		0x1CD4
#define MT6373_RG_LDO_VIBR_RC10_OP_EN_ADDR		0x1CD4
#define MT6373_RG_LDO_VIBR_RC11_OP_EN_ADDR		0x1CD4
#define MT6373_RG_LDO_VIBR_RC12_OP_EN_ADDR		0x1CD4
#define MT6373_RG_LDO_VIBR_RC13_OP_EN_ADDR		0x1CD4
#define MT6373_RG_LDO_VIBR_HW0_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_HW1_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_HW2_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_HW3_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_HW4_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_HW5_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_HW6_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_SW_OP_EN_ADDR		0x1CD5
#define MT6373_RG_LDO_VIBR_RC0_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC1_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC2_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC3_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC4_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC5_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC6_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC7_OP_CFG_ADDR		0x1CD6
#define MT6373_RG_LDO_VIBR_RC8_OP_CFG_ADDR		0x1CD7
#define MT6373_RG_LDO_VIBR_RC9_OP_CFG_ADDR		0x1CD7
#define MT6373_RG_LDO_VIBR_RC10_OP_CFG_ADDR		0x1CD7
#define MT6373_RG_LDO_VIBR_RC11_OP_CFG_ADDR		0x1CD7
#define MT6373_RG_LDO_VIBR_RC12_OP_CFG_ADDR		0x1CD7
#define MT6373_RG_LDO_VIBR_RC13_OP_CFG_ADDR		0x1CD7
#define MT6373_RG_LDO_VIBR_HW0_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_HW1_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_HW2_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_HW3_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_HW4_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_HW5_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_HW6_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_SW_OP_CFG_ADDR		0x1CD8
#define MT6373_RG_LDO_VIBR_RC0_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC1_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC2_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC3_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC4_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC5_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC6_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC7_OP_MODE_ADDR		0x1CD9
#define MT6373_RG_LDO_VIBR_RC8_OP_MODE_ADDR		0x1CDA
#define MT6373_RG_LDO_VIBR_RC9_OP_MODE_ADDR		0x1CDA
#define MT6373_RG_LDO_VIBR_RC10_OP_MODE_ADDR		0x1CDA
#define MT6373_RG_LDO_VIBR_RC11_OP_MODE_ADDR		0x1CDA
#define MT6373_RG_LDO_VIBR_RC12_OP_MODE_ADDR		0x1CDA
#define MT6373_RG_LDO_VIBR_RC13_OP_MODE_ADDR		0x1CDA
#define MT6373_RG_LDO_VIBR_HW0_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIBR_HW1_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIBR_HW2_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIBR_HW3_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIBR_HW4_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIBR_HW5_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIBR_HW6_OP_MODE_ADDR		0x1CDB
#define MT6373_RG_LDO_VIO28_ONLV_EN_ADDR		0x1D08
#define MT6373_RG_LDO_VIO28_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VIO28_RC0_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC1_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC2_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC3_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC4_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC5_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC6_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC7_OP_EN_ADDR		0x1D0C
#define MT6373_RG_LDO_VIO28_RC8_OP_EN_ADDR		0x1D0D
#define MT6373_RG_LDO_VIO28_RC9_OP_EN_ADDR		0x1D0D
#define MT6373_RG_LDO_VIO28_RC10_OP_EN_ADDR		0x1D0D
#define MT6373_RG_LDO_VIO28_RC11_OP_EN_ADDR		0x1D0D
#define MT6373_RG_LDO_VIO28_RC12_OP_EN_ADDR		0x1D0D
#define MT6373_RG_LDO_VIO28_RC13_OP_EN_ADDR		0x1D0D
#define MT6373_RG_LDO_VIO28_HW0_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_HW1_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_HW2_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_HW3_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_HW4_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_HW5_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_HW6_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_SW_OP_EN_ADDR		0x1D0E
#define MT6373_RG_LDO_VIO28_RC0_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC1_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC2_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC3_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC4_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC5_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC6_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC7_OP_CFG_ADDR		0x1D0F
#define MT6373_RG_LDO_VIO28_RC8_OP_CFG_ADDR		0x1D10
#define MT6373_RG_LDO_VIO28_RC9_OP_CFG_ADDR		0x1D10
#define MT6373_RG_LDO_VIO28_RC10_OP_CFG_ADDR		0x1D10
#define MT6373_RG_LDO_VIO28_RC11_OP_CFG_ADDR		0x1D10
#define MT6373_RG_LDO_VIO28_RC12_OP_CFG_ADDR		0x1D10
#define MT6373_RG_LDO_VIO28_RC13_OP_CFG_ADDR		0x1D10
#define MT6373_RG_LDO_VIO28_HW0_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_HW1_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_HW2_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_HW3_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_HW4_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_HW5_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_HW6_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_SW_OP_CFG_ADDR		0x1D11
#define MT6373_RG_LDO_VIO28_RC0_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC1_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC2_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC3_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC4_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC5_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC6_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC7_OP_MODE_ADDR		0x1D12
#define MT6373_RG_LDO_VIO28_RC8_OP_MODE_ADDR		0x1D13
#define MT6373_RG_LDO_VIO28_RC9_OP_MODE_ADDR		0x1D13
#define MT6373_RG_LDO_VIO28_RC10_OP_MODE_ADDR		0x1D13
#define MT6373_RG_LDO_VIO28_RC11_OP_MODE_ADDR		0x1D13
#define MT6373_RG_LDO_VIO28_RC12_OP_MODE_ADDR		0x1D13
#define MT6373_RG_LDO_VIO28_RC13_OP_MODE_ADDR		0x1D13
#define MT6373_RG_LDO_VIO28_HW0_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VIO28_HW1_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VIO28_HW2_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VIO28_HW3_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VIO28_HW4_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VIO28_HW5_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VIO28_HW6_OP_MODE_ADDR		0x1D14
#define MT6373_RG_LDO_VFP_ONLV_EN_ADDR			0x1D16
#define MT6373_RG_LDO_VFP_ONLV_EN_SHIFT			3
#define MT6373_RG_LDO_VFP_RC0_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC1_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC2_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC3_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC4_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC5_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC6_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC7_OP_EN_ADDR		0x1D1A
#define MT6373_RG_LDO_VFP_RC8_OP_EN_ADDR		0x1D1B
#define MT6373_RG_LDO_VFP_RC9_OP_EN_ADDR		0x1D1B
#define MT6373_RG_LDO_VFP_RC10_OP_EN_ADDR		0x1D1B
#define MT6373_RG_LDO_VFP_RC11_OP_EN_ADDR		0x1D1B
#define MT6373_RG_LDO_VFP_RC12_OP_EN_ADDR		0x1D1B
#define MT6373_RG_LDO_VFP_RC13_OP_EN_ADDR		0x1D1B
#define MT6373_RG_LDO_VFP_HW0_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_HW1_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_HW2_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_HW3_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_HW4_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_HW5_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_HW6_OP_EN_ADDR		0x1D1C
#define MT6373_RG_LDO_VFP_SW_OP_EN_ADDR			0x1D1C
#define MT6373_RG_LDO_VFP_RC0_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC1_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC2_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC3_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC4_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC5_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC6_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC7_OP_CFG_ADDR		0x1D1D
#define MT6373_RG_LDO_VFP_RC8_OP_CFG_ADDR		0x1D1E
#define MT6373_RG_LDO_VFP_RC9_OP_CFG_ADDR		0x1D1E
#define MT6373_RG_LDO_VFP_RC10_OP_CFG_ADDR		0x1D1E
#define MT6373_RG_LDO_VFP_RC11_OP_CFG_ADDR		0x1D1E
#define MT6373_RG_LDO_VFP_RC12_OP_CFG_ADDR		0x1D1E
#define MT6373_RG_LDO_VFP_RC13_OP_CFG_ADDR		0x1D1E
#define MT6373_RG_LDO_VFP_HW0_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_HW1_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_HW2_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_HW3_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_HW4_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_HW5_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_HW6_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_SW_OP_CFG_ADDR		0x1D1F
#define MT6373_RG_LDO_VFP_RC0_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC1_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC2_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC3_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC4_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC5_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC6_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC7_OP_MODE_ADDR		0x1D20
#define MT6373_RG_LDO_VFP_RC8_OP_MODE_ADDR		0x1D21
#define MT6373_RG_LDO_VFP_RC9_OP_MODE_ADDR		0x1D21
#define MT6373_RG_LDO_VFP_RC10_OP_MODE_ADDR		0x1D21
#define MT6373_RG_LDO_VFP_RC11_OP_MODE_ADDR		0x1D21
#define MT6373_RG_LDO_VFP_RC12_OP_MODE_ADDR		0x1D21
#define MT6373_RG_LDO_VFP_RC13_OP_MODE_ADDR		0x1D21
#define MT6373_RG_LDO_VFP_HW0_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VFP_HW1_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VFP_HW2_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VFP_HW3_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VFP_HW4_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VFP_HW5_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VFP_HW6_OP_MODE_ADDR		0x1D22
#define MT6373_RG_LDO_VTP_ONLV_EN_ADDR			0x1D24
#define MT6373_RG_LDO_VTP_ONLV_EN_SHIFT			3
#define MT6373_RG_LDO_VTP_RC0_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC1_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC2_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC3_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC4_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC5_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC6_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC7_OP_EN_ADDR		0x1D28
#define MT6373_RG_LDO_VTP_RC8_OP_EN_ADDR		0x1D29
#define MT6373_RG_LDO_VTP_RC9_OP_EN_ADDR		0x1D29
#define MT6373_RG_LDO_VTP_RC10_OP_EN_ADDR		0x1D29
#define MT6373_RG_LDO_VTP_RC11_OP_EN_ADDR		0x1D29
#define MT6373_RG_LDO_VTP_RC12_OP_EN_ADDR		0x1D29
#define MT6373_RG_LDO_VTP_RC13_OP_EN_ADDR		0x1D29
#define MT6373_RG_LDO_VTP_HW0_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_HW1_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_HW2_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_HW3_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_HW4_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_HW5_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_HW6_OP_EN_ADDR		0x1D2A
#define MT6373_RG_LDO_VTP_SW_OP_EN_ADDR			0x1D2A
#define MT6373_RG_LDO_VTP_RC0_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC1_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC2_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC3_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC4_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC5_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC6_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC7_OP_CFG_ADDR		0x1D2B
#define MT6373_RG_LDO_VTP_RC8_OP_CFG_ADDR		0x1D2C
#define MT6373_RG_LDO_VTP_RC9_OP_CFG_ADDR		0x1D2C
#define MT6373_RG_LDO_VTP_RC10_OP_CFG_ADDR		0x1D2C
#define MT6373_RG_LDO_VTP_RC11_OP_CFG_ADDR		0x1D2C
#define MT6373_RG_LDO_VTP_RC12_OP_CFG_ADDR		0x1D2C
#define MT6373_RG_LDO_VTP_RC13_OP_CFG_ADDR		0x1D2C
#define MT6373_RG_LDO_VTP_HW0_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_HW1_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_HW2_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_HW3_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_HW4_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_HW5_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_HW6_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_SW_OP_CFG_ADDR		0x1D2D
#define MT6373_RG_LDO_VTP_RC0_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC1_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC2_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC3_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC4_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC5_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC6_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC7_OP_MODE_ADDR		0x1D2E
#define MT6373_RG_LDO_VTP_RC8_OP_MODE_ADDR		0x1D2F
#define MT6373_RG_LDO_VTP_RC9_OP_MODE_ADDR		0x1D2F
#define MT6373_RG_LDO_VTP_RC10_OP_MODE_ADDR		0x1D2F
#define MT6373_RG_LDO_VTP_RC11_OP_MODE_ADDR		0x1D2F
#define MT6373_RG_LDO_VTP_RC12_OP_MODE_ADDR		0x1D2F
#define MT6373_RG_LDO_VTP_RC13_OP_MODE_ADDR		0x1D2F
#define MT6373_RG_LDO_VTP_HW0_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VTP_HW1_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VTP_HW2_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VTP_HW3_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VTP_HW4_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VTP_HW5_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VTP_HW6_OP_MODE_ADDR		0x1D30
#define MT6373_RG_LDO_VSIM1_ONLV_EN_ADDR		0x1D32
#define MT6373_RG_LDO_VSIM1_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VSIM1_RC0_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC1_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC2_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC3_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC4_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC5_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC6_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC7_OP_EN_ADDR		0x1D36
#define MT6373_RG_LDO_VSIM1_RC8_OP_EN_ADDR		0x1D37
#define MT6373_RG_LDO_VSIM1_RC9_OP_EN_ADDR		0x1D37
#define MT6373_RG_LDO_VSIM1_RC10_OP_EN_ADDR		0x1D37
#define MT6373_RG_LDO_VSIM1_RC11_OP_EN_ADDR		0x1D37
#define MT6373_RG_LDO_VSIM1_RC12_OP_EN_ADDR		0x1D37
#define MT6373_RG_LDO_VSIM1_RC13_OP_EN_ADDR		0x1D37
#define MT6373_RG_LDO_VSIM1_HW0_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_HW1_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_HW2_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_HW3_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_HW4_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_HW5_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_HW6_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_SW_OP_EN_ADDR		0x1D38
#define MT6373_RG_LDO_VSIM1_RC0_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC1_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC2_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC3_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC4_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC5_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC6_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC7_OP_CFG_ADDR		0x1D39
#define MT6373_RG_LDO_VSIM1_RC8_OP_CFG_ADDR		0x1D3A
#define MT6373_RG_LDO_VSIM1_RC9_OP_CFG_ADDR		0x1D3A
#define MT6373_RG_LDO_VSIM1_RC10_OP_CFG_ADDR		0x1D3A
#define MT6373_RG_LDO_VSIM1_RC11_OP_CFG_ADDR		0x1D3A
#define MT6373_RG_LDO_VSIM1_RC12_OP_CFG_ADDR		0x1D3A
#define MT6373_RG_LDO_VSIM1_RC13_OP_CFG_ADDR		0x1D3A
#define MT6373_RG_LDO_VSIM1_HW0_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_HW1_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_HW2_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_HW3_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_HW4_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_HW5_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_HW6_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_SW_OP_CFG_ADDR		0x1D3B
#define MT6373_RG_LDO_VSIM1_RC0_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC1_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC2_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC3_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC4_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC5_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC6_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC7_OP_MODE_ADDR		0x1D3C
#define MT6373_RG_LDO_VSIM1_RC8_OP_MODE_ADDR		0x1D3D
#define MT6373_RG_LDO_VSIM1_RC9_OP_MODE_ADDR		0x1D3D
#define MT6373_RG_LDO_VSIM1_RC10_OP_MODE_ADDR		0x1D3D
#define MT6373_RG_LDO_VSIM1_RC11_OP_MODE_ADDR		0x1D3D
#define MT6373_RG_LDO_VSIM1_RC12_OP_MODE_ADDR		0x1D3D
#define MT6373_RG_LDO_VSIM1_RC13_OP_MODE_ADDR		0x1D3D
#define MT6373_RG_LDO_VSIM1_HW0_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM1_HW1_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM1_HW2_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM1_HW3_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM1_HW4_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM1_HW5_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM1_HW6_OP_MODE_ADDR		0x1D3E
#define MT6373_RG_LDO_VSIM2_ONLV_EN_ADDR		0x1D41
#define MT6373_RG_LDO_VSIM2_ONLV_EN_SHIFT		3
#define MT6373_RG_LDO_VSIM2_RC0_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC1_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC2_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC3_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC4_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC5_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC6_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC7_OP_EN_ADDR		0x1D45
#define MT6373_RG_LDO_VSIM2_RC8_OP_EN_ADDR		0x1D46
#define MT6373_RG_LDO_VSIM2_RC9_OP_EN_ADDR		0x1D46
#define MT6373_RG_LDO_VSIM2_RC10_OP_EN_ADDR		0x1D46
#define MT6373_RG_LDO_VSIM2_RC11_OP_EN_ADDR		0x1D46
#define MT6373_RG_LDO_VSIM2_RC12_OP_EN_ADDR		0x1D46
#define MT6373_RG_LDO_VSIM2_RC13_OP_EN_ADDR		0x1D46
#define MT6373_RG_LDO_VSIM2_HW0_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_HW1_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_HW2_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_HW3_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_HW4_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_HW5_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_HW6_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_SW_OP_EN_ADDR		0x1D47
#define MT6373_RG_LDO_VSIM2_RC0_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC1_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC2_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC3_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC4_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC5_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC6_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC7_OP_CFG_ADDR		0x1D48
#define MT6373_RG_LDO_VSIM2_RC8_OP_CFG_ADDR		0x1D49
#define MT6373_RG_LDO_VSIM2_RC9_OP_CFG_ADDR		0x1D49
#define MT6373_RG_LDO_VSIM2_RC10_OP_CFG_ADDR		0x1D49
#define MT6373_RG_LDO_VSIM2_RC11_OP_CFG_ADDR		0x1D49
#define MT6373_RG_LDO_VSIM2_RC12_OP_CFG_ADDR		0x1D49
#define MT6373_RG_LDO_VSIM2_RC13_OP_CFG_ADDR		0x1D49
#define MT6373_RG_LDO_VSIM2_HW0_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_HW1_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_HW2_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_HW3_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_HW4_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_HW5_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_HW6_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_SW_OP_CFG_ADDR		0x1D4A
#define MT6373_RG_LDO_VSIM2_RC0_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC1_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC2_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC3_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC4_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC5_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC6_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC7_OP_MODE_ADDR		0x1D4B
#define MT6373_RG_LDO_VSIM2_RC8_OP_MODE_ADDR		0x1D4C
#define MT6373_RG_LDO_VSIM2_RC9_OP_MODE_ADDR		0x1D4C
#define MT6373_RG_LDO_VSIM2_RC10_OP_MODE_ADDR		0x1D4C
#define MT6373_RG_LDO_VSIM2_RC11_OP_MODE_ADDR		0x1D4C
#define MT6373_RG_LDO_VSIM2_RC12_OP_MODE_ADDR		0x1D4C
#define MT6373_RG_LDO_VSIM2_RC13_OP_MODE_ADDR		0x1D4C
#define MT6373_RG_LDO_VSIM2_HW0_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSIM2_HW1_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSIM2_HW2_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSIM2_HW3_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSIM2_HW4_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSIM2_HW5_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSIM2_HW6_OP_MODE_ADDR		0x1D4D
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_ADDR	0x1D88
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_SHIFT	3
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_VOSEL_SLEEP_ADDR	0x1D8D
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_EN_ADDR	0x1D94
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_EN_ADDR	0x1D95
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_EN_ADDR	0x1D95
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_EN_ADDR	0x1D95
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_EN_ADDR	0x1D95
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_EN_ADDR	0x1D95
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_EN_ADDR	0x1D95
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_EN_ADDR	0x1D96
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_CFG_ADDR	0x1D97
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_CFG_ADDR	0x1D98
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_CFG_ADDR	0x1D98
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_CFG_ADDR	0x1D98
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_CFG_ADDR	0x1D98
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_CFG_ADDR	0x1D98
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_CFG_ADDR	0x1D98
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_CFG_ADDR	0x1D99
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_MODE_ADDR	0x1D9A
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_MODE_ADDR	0x1D9B
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_MODE_ADDR	0x1D9B
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_MODE_ADDR	0x1D9B
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_MODE_ADDR	0x1D9B
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_MODE_ADDR	0x1D9B
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_MODE_ADDR	0x1D9B
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_MODE_ADDR	0x1D9C
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_MODE_ADDR	0x1D9C
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_MODE_ADDR	0x1D9C
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_MODE_ADDR	0x1D9C
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_MODE_ADDR	0x1D9C
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_MODE_ADDR	0x1D9C
#define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_MODE_ADDR	0x1D9C

#endif /* MT6373_LOWPOWER_REG_H */
