>>> yosys: Building testing/yosys 0.62-r0 (using abuild 3.16.0-r0) started Mon, 09 Feb 2026 15:14:50 +0000 >>> yosys: Validating /home/buildozer/aports/testing/yosys/APKBUILD... >>> yosys: Analyzing dependencies... >>> yosys: Installing for build: build-base abc bash bison boost-dev flex-dev gawk graphviz-dev libffi-dev lld protobuf-dev py3-cxxheaderparser py3-pybind11-dev python3 readline-dev tcl-dev zlib-dev gtkwave iverilog ( 1/360) Installing abc (0_git20240102-r0) ( 2/360) Installing bash (5.3.9-r1) Executing bash-5.3.9-r1.post-install ( 3/360) Installing m4 (1.4.20-r1) ( 4/360) Installing bison (3.8.2-r3) ( 5/360) Installing boost1.84-atomic (1.84.0-r5) ( 6/360) Installing boost1.84-chrono (1.84.0-r5) ( 7/360) Installing boost1.84-container (1.84.0-r5) ( 8/360) Installing boost1.84-context (1.84.0-r5) ( 9/360) Installing boost1.84-contract (1.84.0-r5) ( 10/360) Installing boost1.84-coroutine (1.84.0-r5) ( 11/360) Installing boost1.84-date_time (1.84.0-r5) ( 12/360) Installing boost1.84-fiber (1.84.0-r5) ( 13/360) Installing boost1.84-filesystem (1.84.0-r5) ( 14/360) Installing boost1.84-graph (1.84.0-r5) ( 15/360) Installing libbz2 (1.0.8-r6) ( 16/360) Installing xz-libs (5.8.2-r0) ( 17/360) Installing boost1.84-iostreams (1.84.0-r5) ( 18/360) Installing boost1.84-thread (1.84.0-r5) ( 19/360) Installing icu-data-en (78.1-r0) Executing icu-data-en-78.1-r0.post-install * If you need ICU with non-English locales and legacy charset support, install * package icu-data-full. ( 20/360) Installing icu-libs (78.1-r0) ( 21/360) Installing boost1.84-locale (1.84.0-r5) ( 22/360) Installing boost1.84-log (1.84.0-r5) ( 23/360) Installing boost1.84-log_setup (1.84.0-r5) ( 24/360) Installing boost1.84-math (1.84.0-r5) ( 25/360) Installing boost1.84-prg_exec_monitor (1.84.0-r5) ( 26/360) Installing boost1.84-program_options (1.84.0-r5) ( 27/360) Installing libffi (3.5.2-r0) ( 28/360) Installing gdbm (1.26-r0) ( 29/360) Installing mpdecimal (4.0.1-r0) ( 30/360) Installing libpanelw (6.6_p20251231-r0) ( 31/360) Installing sqlite-libs (3.51.2-r1) ( 32/360) Installing python3 (3.12.12-r0) ( 33/360) Installing python3-pycache-pyc0 (3.12.12-r0) ( 34/360) Installing pyc (3.12.12-r0) ( 35/360) Installing python3-pyc (3.12.12-r0) ( 36/360) Installing boost1.84-python3 (1.84.0-r5) ( 37/360) Installing boost1.84-random (1.84.0-r5) ( 38/360) Installing boost1.84-regex (1.84.0-r5) ( 39/360) Installing boost1.84-serialization (1.84.0-r5) ( 40/360) Installing boost1.84-stacktrace_basic (1.84.0-r5) ( 41/360) Installing boost1.84-stacktrace_noop (1.84.0-r5) ( 42/360) Installing boost1.84-system (1.84.0-r5) ( 43/360) Installing boost1.84-timer (1.84.0-r5) ( 44/360) Installing boost1.84-type_erasure (1.84.0-r5) ( 45/360) Installing boost1.84-unit_test_framework (1.84.0-r5) ( 46/360) Installing boost1.84-url (1.84.0-r5) ( 47/360) Installing boost1.84-wave (1.84.0-r5) ( 48/360) Installing boost1.84-wserialization (1.84.0-r5) ( 49/360) Installing boost1.84-json (1.84.0-r5) ( 50/360) Installing boost1.84-nowide (1.84.0-r5) ( 51/360) Installing boost1.84-libs (1.84.0-r5) ( 52/360) Installing boost1.84 (1.84.0-r5) ( 53/360) Installing linux-headers (6.18.9-r0) ( 54/360) Installing bzip2-dev (1.0.8-r6) ( 55/360) Installing icu (78.1-r0) ( 56/360) Installing icu-dev (78.1-r0) ( 57/360) Installing xz (5.8.2-r0) ( 58/360) Installing xz-dev (5.8.2-r0) ( 59/360) Installing zlib-dev (1.3.1-r2) ( 60/360) Installing zstd (1.5.7-r2) ( 61/360) Installing zstd-dev (1.5.7-r2) ( 62/360) Installing boost1.84-dev (1.84.0-r5) ( 63/360) Installing boost-dev (1.84.0-r5) ( 64/360) Installing flex (2.6.4-r8) ( 65/360) Installing flex-libs (2.6.4-r8) ( 66/360) Installing flex-dev (2.6.4-r8) ( 67/360) Installing gawk (5.3.2-r2) ( 68/360) Installing cairo-tools (1.18.4-r1) ( 69/360) Installing libxau (1.0.12-r0) ( 70/360) Installing libmd (1.1.0-r0) ( 71/360) Installing libbsd (0.12.2-r0) ( 72/360) Installing libxdmcp (1.1.5-r1) ( 73/360) Installing libxcb (1.17.0-r1) ( 74/360) Installing libx11 (1.8.13-r0) ( 75/360) Installing libxext (1.3.7-r0) ( 76/360) Installing libxrender (0.9.12-r0) ( 77/360) Installing libpng (1.6.54-r0) ( 78/360) Installing freetype (2.14.1-r1) ( 79/360) Installing fontconfig (2.17.1-r0) ( 80/360) Installing pixman (0.46.4-r0) ( 81/360) Installing cairo (1.18.4-r1) ( 82/360) Installing libintl (0.24.1-r1) ( 83/360) Installing libeconf (0.8.3-r0) ( 84/360) Installing libblkid (2.41.3-r0) ( 85/360) Installing libmount (2.41.3-r0) ( 86/360) Installing glib (2.86.3-r1) ( 87/360) Installing cairo-gobject (1.18.4-r1) ( 88/360) Installing expat (2.7.4-r0) ( 89/360) Installing expat-dev (2.7.4-r0) ( 90/360) Installing brotli (1.2.0-r0) ( 91/360) Installing brotli-dev (1.2.0-r0) ( 92/360) Installing libpng-dev (1.6.54-r0) ( 93/360) Installing freetype-dev (2.14.1-r1) ( 94/360) Installing fontconfig-dev (2.17.1-r0) ( 95/360) Installing libxml2 (2.13.9-r0) ( 96/360) Installing libxml2-utils (2.13.9-r0) ( 97/360) Installing docbook-xml (4.5-r10) Executing docbook-xml-4.5-r10.post-install ( 98/360) Installing libxslt (1.1.43-r3) ( 99/360) Installing docbook-xsl-ns (1.79.2-r13) Executing docbook-xsl-ns-1.79.2-r13.post-install (100/360) Installing docbook-xsl-nons (1.79.2-r13) Executing docbook-xsl-nons-1.79.2-r13.post-install (101/360) Installing docbook-xsl (1.79.2-r13) (102/360) Installing gettext-asprintf (0.24.1-r1) (103/360) Installing gettext-libs (0.24.1-r1) (104/360) Installing gettext-envsubst (0.24.1-r1) (105/360) Installing gettext (0.24.1-r1) (106/360) Installing gettext-dev (0.24.1-r1) (107/360) Installing py3-parsing (3.3.2-r0) (108/360) Installing py3-parsing-pyc (3.3.2-r0) (109/360) Installing py3-packaging (25.0-r0) (110/360) Installing py3-packaging-pyc (25.0-r0) (111/360) Installing libffi-dev (3.5.2-r0) (112/360) Installing bsd-compat-headers (0.7.2-r6) (113/360) Installing libformw (6.6_p20251231-r0) (114/360) Installing libmenuw (6.6_p20251231-r0) (115/360) Installing libncurses++ (6.6_p20251231-r0) (116/360) Installing ncurses-dev (6.6_p20251231-r0) (117/360) Installing libedit-dev (20251016.3.1-r1) (118/360) Installing libpcre2-16 (10.47-r0) (119/360) Installing libpcre2-32 (10.47-r0) (120/360) Installing pcre2-dev (10.47-r0) (121/360) Installing libuuid (2.41.3-r0) (122/360) Installing libfdisk (2.41.3-r0) (123/360) Installing liblastlog2 (2.41.3-r0) (124/360) Installing libsmartcols (2.41.3-r0) (125/360) Installing sqlite (3.51.2-r1) (126/360) Installing sqlite-dev (3.51.2-r1) (127/360) Installing util-linux-dev (2.41.3-r0) (128/360) Installing glib-dev (2.86.3-r1) (129/360) Installing pixman-dev (0.46.4-r0) (130/360) Installing xorgproto (2025.1-r0) (131/360) Installing libxau-dev (1.0.12-r0) (132/360) Installing xcb-proto (1.17.0-r0) (133/360) Installing xcb-proto-pyc (1.17.0-r0) (134/360) Installing libxdmcp-dev (1.1.5-r1) (135/360) Installing libxcb-dev (1.17.0-r1) (136/360) Installing xtrans (1.6.0-r0) (137/360) Installing libx11-dev (1.8.13-r0) (138/360) Installing libxext-dev (1.3.7-r0) (139/360) Installing libxrender-dev (0.9.12-r0) (140/360) Installing cairo-dev (1.18.4-r1) (141/360) Installing libice (1.1.2-r0) (142/360) Installing libsm (1.2.6-r0) (143/360) Installing libxt (1.3.1-r0) (144/360) Installing libxpm (3.5.18-r0) (145/360) Installing aom-libs (3.13.1-r1) (146/360) Installing libdav1d (1.5.3-r0) (147/360) Installing libjpeg-turbo (3.1.3-r0) (148/360) Installing libyuv (0.0.1887.20251502-r1) (149/360) Installing libavif (1.3.0-r1) (150/360) Installing libsharpyuv (1.6.0-r0) (151/360) Installing libwebp (1.6.0-r0) (152/360) Installing tiff (4.7.1-r0) (153/360) Installing libgd (2.3.3-r10) (154/360) Installing gd (2.3.3-r10) (155/360) Installing perl (5.42.0-r0) (156/360) Installing aom (3.13.1-r1) (157/360) Installing aom-dev (3.13.1-r1) (158/360) Installing dav1d-dev (1.5.3-r0) (159/360) Installing libavif-dev (1.3.0-r1) (160/360) Installing libturbojpeg (3.1.3-r0) (161/360) Installing libjpeg-turbo-dev (3.1.3-r0) (162/360) Installing libtiffxx (4.7.1-r0) (163/360) Installing libwebpdecoder (1.6.0-r0) (164/360) Installing libwebpdemux (1.6.0-r0) (165/360) Installing libwebpmux (1.6.0-r0) (166/360) Installing libwebp-dev (1.6.0-r0) (167/360) Installing tiff-dev (4.7.1-r0) (168/360) Installing libxpm-dev (3.5.18-r0) (169/360) Installing gd-dev (2.3.3-r10) (170/360) Installing libgmpxx (6.3.0-r4) (171/360) Installing gmp-dev (6.3.0-r4) (172/360) Installing libice-dev (1.1.2-r0) (173/360) Installing libsm-dev (1.2.6-r0) (174/360) Installing libxft (2.3.9-r0) (175/360) Installing graphite2 (1.3.14-r6) (176/360) Installing harfbuzz (12.2.0-r1) (177/360) Installing fribidi (1.0.16-r3) (178/360) Installing pango (1.56.4-r0) (179/360) Installing pango-tools (1.56.4-r0) (180/360) Installing fribidi-dev (1.0.16-r3) (181/360) Installing harfbuzz-cairo (12.2.0-r1) (182/360) Installing harfbuzz-gobject (12.2.0-r1) (183/360) Installing harfbuzz-icu (12.2.0-r1) (184/360) Installing harfbuzz-subset (12.2.0-r1) (185/360) Installing graphite2-dev (1.3.14-r6) (186/360) Installing harfbuzz-dev (12.2.0-r1) (187/360) Installing libxft-dev (2.3.9-r0) (188/360) Installing pango-dev (1.56.4-r0) (189/360) Installing python3-dev (3.12.12-r0) (190/360) Installing graphviz-libs (12.2.1-r2) (191/360) Installing graphviz-dev (12.2.1-r2) (192/360) Installing llvm21-libs (21.1.8-r0) (193/360) Installing lld21-libs (21.1.8-r0) (194/360) Installing scudo-malloc (21.1.8-r0) (195/360) Installing lld21 (21.1.8-r0) (196/360) Installing abseil-cpp-raw-logging-internal (20250814.1-r0) (197/360) Installing abseil-cpp-crc-internal (20250814.1-r0) (198/360) Installing abseil-cpp-crc32c (20250814.1-r0) (199/360) Installing abseil-cpp-crc-cord-state (20250814.1-r0) (200/360) Installing abseil-cpp-strings-internal (20250814.1-r0) (201/360) Installing abseil-cpp-strings (20250814.1-r0) (202/360) Installing abseil-cpp-cord-internal (20250814.1-r0) (203/360) Installing abseil-cpp-exponential-biased (20250814.1-r0) (204/360) Installing abseil-cpp-cordz-functions (20250814.1-r0) (205/360) Installing abseil-cpp-spinlock-wait (20250814.1-r0) (206/360) Installing abseil-cpp-base (20250814.1-r0) (207/360) Installing abseil-cpp-time-zone (20250814.1-r0) (208/360) Installing abseil-cpp-time (20250814.1-r0) (209/360) Installing abseil-cpp-kernel-timeout-internal (20250814.1-r0) (210/360) Installing abseil-cpp-malloc-internal (20250814.1-r0) (211/360) Installing abseil-cpp-debugging-internal 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(20250814.1-r0) (228/360) Installing abseil-cpp-log-globals (20250814.1-r0) (229/360) Installing abseil-cpp-int128 (20250814.1-r0) (230/360) Installing abseil-cpp-str-format-internal (20250814.1-r0) (231/360) Installing abseil-cpp-log-internal-format (20250814.1-r0) (232/360) Installing abseil-cpp-log-sink (20250814.1-r0) (233/360) Installing abseil-cpp-log-internal-log-sink-set (20250814.1-r0) (234/360) Installing abseil-cpp-log-internal-proto (20250814.1-r0) (235/360) Installing abseil-cpp-log-internal-structured-proto (20250814.1-r0) (236/360) Installing abseil-cpp-strerror (20250814.1-r0) (237/360) Installing abseil-cpp-log-internal-message (20250814.1-r0) (238/360) Installing abseil-cpp-hashtablez-sampler (20250814.1-r0) (239/360) Installing abseil-cpp-raw-hash-set (20250814.1-r0) (240/360) Installing abseil-cpp-status (20250814.1-r0) (241/360) Installing abseil-cpp-statusor (20250814.1-r0) (242/360) Installing abseil-cpp-throw-delegate (20250814.1-r0) (243/360) Installing abseil-cpp-die-if-null (20250814.1-r0) (244/360) Installing libprotobuf-lite (31.1-r1) (245/360) Installing protobuf (31.1-r1) (246/360) Installing libprotobuf (31.1-r1) (247/360) Installing libprotoc (31.1-r1) (248/360) Installing protoc (31.1-r1) (249/360) Installing abseil-cpp-civil-time (20250814.1-r0) (250/360) Installing abseil-cpp-cordz-sample-token (20250814.1-r0) (251/360) Installing abseil-cpp-crc-cpu-detect (20250814.1-r0) (252/360) Installing abseil-cpp-utf8-for-code-point (20250814.1-r0) (253/360) Installing abseil-cpp-decode-rust-punycode (20250814.1-r0) (254/360) Installing abseil-cpp-demangle-rust (20250814.1-r0) (255/360) Installing abseil-cpp-demangle-internal (20250814.1-r0) (256/360) Installing gtest (1.17.0-r0) (257/360) Installing abseil-cpp-exception-safety-testing (20250814.1-r0) (258/360) Installing abseil-cpp-failure-signal-handler (20250814.1-r0) (259/360) Installing abseil-cpp-flags-commandlineflag-internal (20250814.1-r0) (260/360) Installing abseil-cpp-flags-commandlineflag (20250814.1-r0) (261/360) Installing abseil-cpp-flags-program-name (20250814.1-r0) (262/360) Installing abseil-cpp-flags-config (20250814.1-r0) (263/360) Installing abseil-cpp-flags-internal (20250814.1-r0) (264/360) Installing abseil-cpp-flags-marshalling (20250814.1-r0) (265/360) Installing abseil-cpp-flags-private-handle-accessor (20250814.1-r0) (266/360) Installing abseil-cpp-flags-reflection (20250814.1-r0) (267/360) Installing abseil-cpp-flags-usage (20250814.1-r0) (268/360) Installing abseil-cpp-flags-usage-internal (20250814.1-r0) (269/360) Installing abseil-cpp-flags-parse (20250814.1-r0) (270/360) Installing abseil-cpp-graphcycles-internal (20250814.1-r0) (271/360) Installing abseil-cpp-random-internal-randen-hwaes (20250814.1-r0) (272/360) Installing abseil-cpp-random-internal-randen-hwaes-impl (20250814.1-r0) (273/360) Installing abseil-cpp-random-internal-platform (20250814.1-r0) (274/360) Installing abseil-cpp-random-internal-randen-slow (20250814.1-r0) (275/360) Installing abseil-cpp-random-internal-randen (20250814.1-r0) (276/360) Installing abseil-cpp-random-internal-seed-material (20250814.1-r0) (277/360) Installing abseil-cpp-random-seed-gen-exception (20250814.1-r0) (278/360) Installing abseil-cpp-random-internal-entropy-pool (20250814.1-r0) (279/360) Installing abseil-cpp-hash-generator-testing (20250814.1-r0) (280/360) Installing abseil-cpp-profile-builder (20250814.1-r0) (281/360) Installing abseil-cpp-hashtable-profiler (20250814.1-r0) (282/360) Installing abseil-cpp-log-severity (20250814.1-r0) (283/360) Installing abseil-cpp-log-entry (20250814.1-r0) (284/360) Installing abseil-cpp-log-internal-fnmatch (20250814.1-r0) (285/360) Installing abseil-cpp-vlog-config-internal (20250814.1-r0) (286/360) Installing abseil-cpp-log-flags (20250814.1-r0) (287/360) Installing abseil-cpp-log-internal-test-actions (20250814.1-r0) (288/360) Installing abseil-cpp-log-internal-test-helpers (20250814.1-r0) (289/360) Installing abseil-cpp-log-internal-test-matchers (20250814.1-r0) (290/360) Installing abseil-cpp-per-thread-sem-test-common (20250814.1-r0) (291/360) Installing abseil-cpp-periodic-sampler (20250814.1-r0) (292/360) Installing abseil-cpp-poison (20250814.1-r0) (293/360) Installing abseil-cpp-pow10-helper (20250814.1-r0) (294/360) Installing abseil-cpp-random-distributions (20250814.1-r0) (295/360) Installing abseil-cpp-random-internal-distribution-test-util (20250814.1-r0) (296/360) Installing abseil-cpp-random-seed-sequences (20250814.1-r0) (297/360) Installing gmock (1.17.0-r0) (298/360) Installing abseil-cpp-scoped-mock-log (20250814.1-r0) (299/360) Installing abseil-cpp-scoped-set-env (20250814.1-r0) (300/360) Installing abseil-cpp-spinlock-test-common (20250814.1-r0) (301/360) Installing abseil-cpp-stack-consumption (20250814.1-r0) (302/360) Installing abseil-cpp-status-matchers (20250814.1-r0) (303/360) Installing abseil-cpp-string-view (20250814.1-r0) (304/360) Installing abseil-cpp-test-instance-tracker (20250814.1-r0) (305/360) Installing abseil-cpp-time-internal-test-util (20250814.1-r0) (306/360) Installing abseil-cpp-dev (20250814.1-r0) (307/360) Installing protobuf-dev (31.1-r1) (308/360) Installing py3-cxxheaderparser (1.7.0-r0) (309/360) Installing py3-cxxheaderparser-pyc (1.7.0-r0) (310/360) Installing py3-pybind11 (3.0.1-r0) (311/360) Installing py3-pybind11-pyc (3.0.1-r0) (312/360) Installing py3-pybind11-dev (3.0.1-r0) (313/360) Installing libhistory (8.3.3-r1) (314/360) Installing readline-dev (8.3.3-r1) (315/360) Installing tzdata (2025c-r0) (316/360) Installing tcl (8.6.17-r0) (317/360) Installing tcl-dev (8.6.17-r0) (318/360) Installing desktop-file-utils (0.28-r0) (319/360) Installing gobject-introspection (1.86.0-r0) (320/360) Installing shared-mime-info (2.4-r7) (321/360) Installing libxcomposite (0.4.7-r0) (322/360) Installing libxfixes (6.0.2-r0) (323/360) Installing libxcursor (1.2.3-r0) (324/360) Installing libxdamage (1.1.7-r0) (325/360) Installing libxi (1.8.2-r0) (326/360) Installing libxinerama (1.1.6-r0) (327/360) Installing libxrandr (1.5.5-r0) (328/360) Installing libatk-1.0 (2.58.3-r0) (329/360) Installing dbus-libs (1.16.2-r1) (330/360) Installing at-spi2-core-libs (2.58.3-r0) (331/360) Installing libxtst (1.2.5-r0) (332/360) Installing at-spi2-core (2.58.3-r0) (333/360) Installing libatk-bridge-2.0 (2.58.3-r0) (334/360) Installing avahi-libs (0.8-r23) (335/360) Installing nettle (3.10.2-r0) (336/360) Installing libtasn1 (4.21.0-r0) (337/360) Installing p11-kit (0.25.5-r2) (338/360) Installing gnutls (3.8.11-r0) (339/360) Installing cups-libs (2.4.16-r0) (340/360) Installing libepoxy (1.5.10-r1) (341/360) Installing bubblewrap (0.11.0-r3) (342/360) Installing lcms2 (2.17-r0) (343/360) Installing libseccomp (2.6.0-r1) (344/360) Installing libglycin (2.0.7-r1) Executing libglycin-2.0.7-r1.post-install * glycin loaders got split into their individual subpackages. * By default, only glycin-image-rs & glycin-svg are installed. * Additional loader subpackages are glycin-heif, glycin-jxl & glycin-raw. * * To install all available loaders, install glycin-loaders-all. * * Also the glycin-thumbnailer got subpackaged and isn't installed by default. (345/360) Installing glycin-image-rs (2.0.7-r11) (346/360) Installing librsvg (2.61.3-r2) (347/360) Installing glycin-svg (2.0.7-r11) (348/360) Installing gdk-pixbuf (2.44.5-r0) (349/360) Installing wayland-libs-client (1.24.0-r0) (350/360) Installing wayland-libs-cursor (1.24.0-r0) (351/360) Installing wayland-libs-egl (1.24.0-r0) (352/360) Installing xkeyboard-config (2.46-r0) (353/360) Installing libxkbcommon (1.12.2-r0) (354/360) Installing gtk+3.0 (3.24.51-r3) (355/360) Installing gtkwave (3.3.120-r0) (356/360) Installing iverilog (12.0-r3) (357/360) Installing .makedepends-yosys (20260209.151451) (358/360) Installing perl-error (0.17030-r0) (359/360) Installing perl-git (2.53.0-r0) (360/360) Installing git-perl (2.53.0-r0) Executing busybox-1.37.0-r31.trigger Executing glib-2.86.3-r1.trigger Executing desktop-file-utils-0.28-r0.trigger Executing shared-mime-info-2.4-r7.trigger Executing gdk-pixbuf-2.44.5-r0.trigger Executing gtk+3.0-3.24.51-r3.trigger OK: 1097.4 MiB in 467 packages >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Cleaning up tmpdir >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.62.tar.gz Connecting to distfiles.alpinelinux.org (172.105.82.32:443) wget: server returned error: HTTP/1.1 404 Not Found >>> yosys: Fetching yosys-0.62.tar.gz::https://github.com/YosysHQ/yosys/releases/download/v0.62/yosys.tar.gz Connecting to github.com (140.82.121.3:443) Connecting to release-assets.githubusercontent.com (185.199.108.133:443) saving to '/var/cache/distfiles/edge/yosys-0.62.tar.gz.part' yosys-0.62.tar.gz.pa 100% |********************************| 10.4M 0:00:00 ETA '/var/cache/distfiles/edge/yosys-0.62.tar.gz.part' saved /var/cache/distfiles/edge/yosys-0.62.tar.gz: OK /home/buildozer/aports/testing/yosys/fix-32-bit-oom.patch: OK /home/buildozer/aports/testing/yosys/skip-xaiger2-5169-test.patch: OK >>> yosys: Fetching https://distfiles.alpinelinux.org/distfiles/edge/yosys-0.62.tar.gz /var/cache/distfiles/edge/yosys-0.62.tar.gz: OK /home/buildozer/aports/testing/yosys/fix-32-bit-oom.patch: OK /home/buildozer/aports/testing/yosys/skip-xaiger2-5169-test.patch: OK >>> yosys: Unpacking /var/cache/distfiles/edge/yosys-0.62.tar.gz... >>> yosys: fix-32-bit-oom.patch patching file Makefile Hunk #1 succeeded at 773 (offset -9 lines). >>> yosys: skip-xaiger2-5169-test.patch patching file tests/techmap/xaiger2-5169.ys [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=/usr/bin/abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_ABC:=1 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] PYOSYS_USE_UV:=0 [ 0%] Building kernel/version_7326bb7d6641500ecb285c291a54a662cb1e76cf.cc [ 0%] Building pyosys/wrappers.cc [ 0%] Building kernel/driver.o [ 0%] Building techlibs/common/simlib_help.inc [ 0%] Building techlibs/common/simcells_help.inc [ 1%] Building kernel/rtlil.o [ 1%] Building kernel/log.o [ 1%] Building kernel/calc.o [ 2%] Building kernel/yosys.o [ 2%] Building kernel/io.o [ 2%] Building kernel/gzip.o [ 2%] Building kernel/rtlil_bufnorm.o [ 3%] Building kernel/log_help.o [ 3%] Building kernel/binding.o [ 3%] Building kernel/tclapi.o [ 4%] Building kernel/cellaigs.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/binding.h [ 4%] Building kernel/celledges.o [ 4%] Building kernel/cost.o [ 4%] Building kernel/satgen.o [ 5%] Building kernel/scopeinfo.o [ 5%] Building kernel/qcsat.o [ 5%] Building kernel/mem.o [ 5%] Building kernel/ffmerge.o [ 6%] Building kernel/ff.o [ 6%] Building kernel/yw.o [ 6%] Building kernel/json.o [ 6%] Building kernel/fmt.o [ 7%] Building kernel/sexpr.o [ 7%] Building kernel/drivertools.o [ 7%] Building kernel/functional.o [ 8%] Building kernel/threading.o [ 8%] Building kernel/fstdata.o [ 8%] Building libs/bigint/BigIntegerAlgorithms.o [ 8%] Building libs/bigint/BigInteger.o [ 9%] Building libs/bigint/BigIntegerUtils.o [ 9%] Building libs/bigint/BigUnsigned.o [ 9%] Building libs/bigint/BigUnsignedInABase.o [ 9%] Building libs/sha1/sha1.o [ 10%] Building libs/json11/json11.o [ 10%] Building libs/ezsat/ezsat.o [ 10%] Building libs/ezsat/ezminisat.o [ 11%] Building libs/minisat/Options.o [ 11%] Building libs/minisat/SimpSolver.o [ 11%] Building libs/minisat/Solver.o [ 11%] Building libs/minisat/System.o [ 12%] Building libs/fst/fstapi.o [ 12%] Building libs/fst/fastlz.o [ 12%] Building libs/fst/lz4.o [ 12%] Building libs/subcircuit/subcircuit.o [ 13%] Building frontends/aiger/aigerparse.o [ 13%] Building frontends/aiger2/xaiger.o [ 13%] Building frontends/ast/ast.o In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:125:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' 125 | capacity(size); | ~~~~~~~~^~~~~~ libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]' 48 | void reserve(K key) { map.growTo(index(key)+1); } | ~~~~~~~~~~^~~~~~~~~~~~~~ libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]' 338 | void init (const K& idx){ occs.reserve(idx); occs[idx].clear(); dirty.reserve(idx, 0); } | ~~~~~~~~~~~~^~~~~ libs/minisat/SimpSolver.cc:92:26: required from here 92 | occurs .init (v); | ~~~~~~~~~~~~~~~~~^~~ libs/minisat/Vec.h:107:35: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 107 | ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 13%] Building frontends/ast/simplify.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/libs/sha1/sha1.h [ 14%] Building frontends/ast/genrtlil.o In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:125:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' 125 | capacity(size); | ~~~~~~~~^~~~~~ libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]' 48 | void reserve(K key) { map.growTo(index(key)+1); } | ~~~~~~~~~~^~~~~~~~~~~~~~ libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]' 338 | void init (const K& idx){ occs.reserve(idx); occs[idx].clear(); dirty.reserve(idx, 0); } | ~~~~~~~~~~~~^~~~~ libs/minisat/Solver.cc:134:19: required from here 134 | watches .init(mkLit(v, false)); | ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:107:35: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 107 | ((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ [ 14%] Building frontends/ast/dpicall.o [ 14%] Building frontends/ast/ast_binding.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/log.h [ 15%] Building frontends/blif/blifparse.o [ 15%] Building frontends/json/jsonparse.o [ 15%] Building frontends/liberty/liberty.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/yosys.h [ 15%] Building frontends/rpc/rpc_frontend.o [ 16%] Building frontends/rtlil/rtlil_frontend.o kernel/fmt.cc: In member function 'std::string Yosys::Fmt::render() const': kernel/fmt.cc:808:78: warning: left operand of comma operator has no effect [-Wunused-value] 808 | buf += (part.hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[subvalue.as_int()]; | ~~~~~^~~~~~~~~ + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/cost.h [ 16%] Building frontends/verific/verific.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/celltypes.h [ 16%] Building frontends/verilog/verilog_parser.tab.cc [ 17%] Building frontends/verilog/verilog_error.o [ 18%] Building frontends/verilog/const2ast.o In file included from /usr/lib/python3.12/site-packages/pybind11/include/pybind11/attr.h:13, from /usr/lib/python3.12/site-packages/pybind11/include/pybind11/detail/class.h:12, from /usr/lib/python3.12/site-packages/pybind11/include/pybind11/pybind11.h:12, from kernel/yosys.cc:43: kernel/yosys.cc: In function 'void Yosys::pybind11_init_libyosys_dummy(pybind11::module_&)': kernel/yosys.cc:230:33: warning: unused parameter '_' [-Wunused-parameter] 230 | PYBIND11_MODULE(libyosys_dummy, _) { /usr/lib/python3.12/site-packages/pybind11/include/pybind11/detail/common.h:468:50: note: in definition of macro 'PYBIND11_MODULE_EXEC' 468 | & variable) // NOLINT(bugprone-macro-parentheses) | ^~~~~~~~ kernel/yosys.cc:230:1: note: in expansion of macro 'PYBIND11_MODULE' 230 | PYBIND11_MODULE(libyosys_dummy, _) { | ^~~~~~~~~~~~~~~ [ 18%] Building passes/cmds/exec.o [ 18%] Building passes/cmds/add.o [ 18%] Building passes/cmds/delete.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/consteval.h [ 19%] Building passes/cmds/design.o [ 19%] Building passes/cmds/design_equal.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from ./kernel/cost.h:23, from kernel/cost.cc:1: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'void std::__new_allocator<_Tp>::construct(_Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/new_allocator.h:191:4, inlined from 'static void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:674:17, inlined from 'void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from kernel/cost.cc:2: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'void std::__new_allocator<_Tp>::construct(_Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/new_allocator.h:191:4, inlined from 'static void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:674:17, inlined from 'void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/register.h [ 19%] Building passes/cmds/select.o + g++ -fsyntax-only -std=c++17 -w -E -C -I/home/buildozer/aports/testing/yosys/src -I/usr/include/python3.12 -I/usr/lib/python3.12/site-packages/pybind11/include -D_YOSYS_ -DYOSYS_ENABLE_PYTHON /home/buildozer/aports/testing/yosys/src/kernel/rtlil.h [ 19%] Building passes/cmds/show.o [ 20%] Building passes/cmds/viz.o kernel/drivertools.cc: In member function 'bool Yosys::DriveChunkMultiple::try_append(const Yosys::DriveBitMultiple&)': kernel/drivertools.cc:263:79: warning: 'constant' may be used uninitialized [-Wmaybe-uninitialized] 263 | single.constant().append(RTLIL::Const(constant)); | ^ kernel/drivertools.cc:252:15: note: 'constant' was declared here 252 | State constant; | ^~~~~~~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from frontends/aiger2/xaiger.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 20%] Building passes/cmds/rename.o [ 20%] Building passes/cmds/autoname.o [ 20%] Building passes/cmds/connect.o [ 21%] Building passes/cmds/scatter.o [ 21%] Building passes/cmds/setundef.o [ 21%] Building passes/cmds/splitnets.o [ 22%] Building passes/cmds/splitcells.o [ 22%] Building passes/cmds/stat.o [ 22%] Building passes/cmds/internal_stats.o In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::Xaiger2Frontend::read_sc_mapping(std::istream*&, std::string, std::vector >, Yosys::RTLIL::Design*)' at frontends/aiger2/xaiger.cc:220:50: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'void {anonymous}::Xaiger2Frontend::read_sc_mapping(std::istream*&, std::string, std::vector >, Yosys::RTLIL::Design*)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::Xaiger2Frontend::read_sc_mapping(std::istream*&, std::string, std::vector >, Yosys::RTLIL::Design*)' at frontends/aiger2/xaiger.cc:220:50: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'void {anonymous}::Xaiger2Frontend::read_sc_mapping(std::istream*&, std::string, std::vector >, Yosys::RTLIL::Design*)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 22%] Building passes/cmds/setattr.o [ 23%] Building passes/cmds/copy.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23, from ./kernel/satgen.h:23, from kernel/satgen.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'void std::__new_allocator<_Tp>::construct(_Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/new_allocator.h:191:4, inlined from 'static void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:674:17, inlined from 'void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/satgen.h:26: ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'Yosys::Macc::term_t::term_t(Yosys::Macc::term_t&&)' at ./kernel/macc.h:29:9, inlined from 'void std::__new_allocator<_Tp>::construct(_Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/new_allocator.h:191:4, inlined from 'static void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = Yosys::Macc::term_t; _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:674:17, inlined from 'void std::vector<_Tp, _Alloc>::_M_realloc_append(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:586:26, inlined from 'std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {Yosys::Macc::term_t}; _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:123:21, inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = Yosys::Macc::term_t; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)' at ./kernel/macc.h:133:19: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::Macc::term_t, Yosys::Macc::term_t::in_b.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/macc.h: In member function 'void Yosys::Macc::from_cell_v1(Yosys::RTLIL::Cell*)': ./kernel/macc.h:133:71: note: '' declared here 133 | terms.push_back(term_t{{bit}, {}, false, false}); | ^ [ 23%] Building passes/cmds/splice.o [ 23%] Building passes/cmds/scc.o [ 23%] Building passes/cmds/glift.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from kernel/rtlil_bufnorm.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:535:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:680:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:535:67: note: '' declared here 535 | entries.emplace_back(std::pair(key, T()), -1); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:535:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:680:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:535:67: note: '' declared here 535 | entries.emplace_back(std::pair(key, T()), -1); | ^~~ In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:538:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:680:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:538:67: note: '' declared here 538 | entries.emplace_back(std::pair(key, T()), hashtable[hash]); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'int Yosys::hashlib::dict::do_insert(const K&, const Yosys::hashlib::HasherDJB32::hash_t&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:538:30, inlined from 'std::pair::iterator, bool> Yosys::hashlib::dict::insert(const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:680:16, inlined from 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)' at kernel/rtlil_bufnorm.cc:591:30: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'void Yosys::RTLIL::Cell::setPort(Yosys::RTLIL::IdString, Yosys::RTLIL::SigSpec)': ./kernel/hashlib.h:538:67: note: '' declared here 538 | entries.emplace_back(std::pair(key, T()), hashtable[hash]); | ^~~ [ 24%] Building passes/cmds/torder.o [ 24%] Building passes/cmds/logcmd.o [ 24%] Building passes/cmds/tee.o [ 24%] Building passes/cmds/write_file.o [ 25%] Building passes/cmds/connwrappers.o [ 25%] Building passes/cmds/trace.o [ 25%] Building passes/cmds/plugin.o [ 26%] Building passes/cmds/check.o [ 26%] Building passes/cmds/edgetypes.o [ 26%] Building passes/cmds/portlist.o [ 26%] Building passes/cmds/chformal.o [ 27%] Building passes/cmds/chtype.o [ 27%] Building passes/cmds/blackbox.o [ 27%] Building passes/cmds/ltp.o [ 27%] Building passes/cmds/linux_perf.o [ 28%] Building passes/cmds/bugpoint.o [ 28%] Building passes/cmds/scratchpad.o [ 28%] Building passes/cmds/logger.o [ 29%] Building passes/cmds/printattrs.o [ 29%] Building passes/cmds/sta.o [ 29%] Building passes/cmds/clean_zerowidth.o [ 29%] Building passes/cmds/xprop.o [ 30%] Building passes/cmds/dft_tag.o [ 30%] Building passes/cmds/future.o [ 30%] Building passes/cmds/box_derive.o [ 30%] Building passes/cmds/example_dt.o [ 31%] Building passes/cmds/portarcs.o [ 31%] Building passes/cmds/wrapcell.o [ 31%] Building passes/cmds/setenv.o [ 31%] Building passes/cmds/abstract.o [ 32%] Building passes/cmds/test_select.o [ 32%] Building passes/cmds/timeest.o [ 32%] Building passes/cmds/linecoverage.o [ 33%] Building passes/cmds/sort.o [ 33%] Building passes/cmds/icell_liberty.o [ 33%] Building passes/cmds/sdc/sdc.o [ 33%] Building passes/equiv/equiv_make.o [ 34%] Building passes/equiv/equiv_miter.o [ 34%] Building passes/equiv/equiv_simple.o [ 34%] Building passes/equiv/equiv_status.o In file included from ./kernel/yosys.h:42, from passes/cmds/abstract.cc:1: passes/cmds/abstract.cc: In member function 'virtual void {anonymous}::AbstractPass::execute(std::vector >, Yosys::RTLIL::Design*)': ./kernel/log.h:283:77: warning: this statement may fall through [-Wimplicit-fallthrough=] 283 | # define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__) passes/cmds/abstract.cc:471:41: note: in expansion of macro 'log_assert' 471 | log_assert(false); | ^~~~~~~~~~ passes/cmds/abstract.cc:472:33: note: here 472 | case Enable::ActiveLow: | ^~~~ [ 34%] Building passes/equiv/equiv_add.o [ 35%] Building passes/equiv/equiv_remove.o [ 35%] Building passes/equiv/equiv_induct.o passes/equiv/equiv_make.cc: In member function 'void {anonymous}::EquivMakeWorker::read_encfiles()': passes/equiv/equiv_make.cc:81:50: warning: variable 'modname' set but not used [-Wunused-but-set-variable] 81 | IdString modname = RTLIL::escape_id(next_token(line)); | ^~~~~~~ [ 35%] Building passes/equiv/equiv_struct.o [ 36%] Building passes/equiv/equiv_purge.o [ 36%] Building passes/equiv/equiv_mark.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/cmds/scc.cc:24: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 36%] Building passes/equiv/equiv_opt.o [ 36%] Building passes/fsm/fsm.o [ 37%] Building passes/fsm/fsm_detect.o [ 37%] Building passes/fsm/fsm_extract.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/cmds/wrapcell.cc:19: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 37%] Building passes/fsm/fsm_opt.o [ 37%] Building passes/fsm/fsm_expand.o [ 38%] Building passes/fsm/fsm_recode.o [ 38%] Building passes/fsm/fsm_info.o [ 38%] Building passes/fsm/fsm_export.o [ 38%] Building passes/fsm/fsm_map.o [ 39%] Building passes/hierarchy/flatten.o [ 39%] Building passes/hierarchy/hierarchy.o [ 39%] Building passes/hierarchy/uniquify.o [ 40%] Building passes/hierarchy/submod.o [ 40%] Building passes/hierarchy/keep_hierarchy.o [ 40%] Building passes/memory/memory.o [ 40%] Building passes/memory/memory_dff.o [ 41%] Building passes/memory/memory_share.o [ 41%] Building passes/memory/memory_collect.o [ 41%] Building passes/memory/memory_unpack.o [ 41%] Building passes/memory/memory_bram.o [ 42%] Building passes/memory/memory_map.o [ 42%] Building passes/memory/memory_memx.o [ 42%] Building passes/memory/memory_nordff.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/cmds/sdc/sdc.cc:3: In destructor 'std::_Vector_base<_Tp, _Alloc>::~_Vector_base() [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::vector<_Tp, _Alloc>::~vector() [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:805:7, inlined from 'Yosys::RTLIL::SigChunk::~SigChunk()' at ./kernel/rtlil.h:1283:15, inlined from 'void Yosys::RTLIL::SigSpec::destroy()' at ./kernel/rtlil.h:1448:20, inlined from 'void Yosys::RTLIL::SigSpec::destroy()' at ./kernel/rtlil.h:1446:7, inlined from 'Yosys::RTLIL::SigSpec::~SigSpec()' at ./kernel/rtlil.h:1485:10, inlined from 'std::pair::~pair()' at /usr/include/c++/15.2.0/bits/stl_pair.h:302:12, inlined from 'void {anonymous}::SdcObjects::sniff_module(std::__cxx11::list >&, Yosys::RTLIL::Module*)' at passes/cmds/sdc/sdc.cc:155:4: /usr/include/c++/15.2.0/bits/stl_vector.h:376:49: warning: '*(std::_Vector_base >*)((char*)&pin + offsetof(std::pair,std::pair::second.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_M_impl.std::_Vector_base >::_Vector_impl::std::_Vector_base >::_Vector_impl_data.std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 376 | _M_impl._M_end_of_storage - _M_impl._M_start); | ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ passes/cmds/sdc/sdc.cc: In member function 'void {anonymous}::SdcObjects::sniff_module(std::__cxx11::list >&, Yosys::RTLIL::Module*)': passes/cmds/sdc/sdc.cc:151:35: note: '*(std::_Vector_base >*)((char*)&pin + offsetof(std::pair,std::pair::second.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_M_impl.std::_Vector_base >::_Vector_impl::std::_Vector_base >::_Vector_impl_data.std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' was declared here 151 | for (auto pin : cell->connections()) { | ^~~ [ 42%] Building passes/memory/memory_narrow.o [ 43%] Building passes/memory/memory_libmap.o [ 43%] Building passes/memory/memory_bmux2rom.o [ 43%] Building passes/memory/memlib.o [ 44%] Building passes/opt/opt.o [ 44%] Building passes/opt/opt_merge.o [ 44%] Building passes/opt/opt_mem.o [ 44%] Building passes/opt/opt_mem_feedback.o [ 45%] Building passes/opt/opt_mem_priority.o [ 45%] Building passes/opt/opt_mem_widen.o In file included from /usr/include/c++/15.2.0/string:56, from ./kernel/yosys_common.h:29: In member function 'bool std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::_M_is_local() const [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]', inlined from 'std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::basic_string(std::__cxx11::basic_string<_CharT, _Traits, _Alloc>&&) [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/basic_string.h:745:23, inlined from 'constexpr std::__detail::__variant::_Uninitialized<_Type, false>::_Uninitialized(std::in_place_index_t<0>, _Args&& ...) [with _Args = {std::__cxx11::basic_string, std::allocator >}; _Type = std::__cxx11::basic_string]' at /usr/include/c++/15.2.0/variant:260:4, inlined from 'constexpr std::__detail::__variant::_Variadic_union<__trivially_destructible, _First, _Rest ...>::_Variadic_union(std::in_place_index_t<0>, _Args&& ...) [with _Args = {std::__cxx11::basic_string, std::allocator >}; bool __trivially_destructible = false; _First = std::__cxx11::basic_string; _Rest = {}]' at /usr/include/c++/15.2.0/variant:404:4, inlined from 'constexpr std::__detail::__variant::_Variadic_union<__trivially_destructible, _First, _Rest ...>::_Variadic_union(std::in_place_index_t<_Np>, _Args&& ...) [with long unsigned int _Np = 1; _Args = {std::__cxx11::basic_string, std::allocator >}; bool __trivially_destructible = false; _First = {anonymous}::SdcGraphNode*; _Rest = {std::__cxx11::basic_string, std::allocator >}]' at /usr/include/c++/15.2.0/variant:410:4, inlined from 'void std::_Construct(_Tp*, _Args&& ...) [with _Tp = __detail::__variant::_Variadic_union, allocator > >; _Args = {const in_place_index_t<1>&, __cxx11::basic_string, allocator >}]' at /usr/include/c++/15.2.0/bits/stl_construct.h:133:7, inlined from 'std::__detail::__variant::_Move_ctor_base, std::allocator > >::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base, std::allocator > >&&):: mutable [with auto:4 = std::__cxx11::basic_string; auto:5 = std::integral_constant]' at /usr/include/c++/15.2.0/variant:627:23, inlined from 'constexpr _Res std::__invoke_impl(__invoke_other, _Fn&&, _Args&& ...) [with _Res = void; _Fn = __detail::__variant::_Move_ctor_base, allocator > >::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base, std::allocator > >&&)::; _Args = {__cxx11::basic_string, allocator >, integral_constant}]' at /usr/include/c++/15.2.0/bits/invoke.h:63:36, inlined from 'constexpr typename std::__invoke_result<_Functor, _ArgTypes>::type std::__invoke(_Callable&&, _Args&& ...) [with _Callable = __detail::__variant::_Move_ctor_base, allocator > >::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base, std::allocator > >&&)::; _Args = {__cxx11::basic_string, allocator >, integral_constant}]' at /usr/include/c++/15.2.0/bits/invoke.h:98:40, inlined from 'static constexpr decltype(auto) std::__detail::__variant::__gen_vtable_impl, std::integer_sequence >::__visit_invoke(_Visitor&&, _Variants ...) [with _Result_type = std::__detail::__variant::__variant_idx_cookie; _Visitor = std::__detail::__variant::_Move_ctor_base, std::allocator > >::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base, std::allocator > >&&)::&&; _Variants = {std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >&&}; long unsigned int ...__indices = {1}]' at /usr/include/c++/15.2.0/variant:1044:17, inlined from 'constexpr decltype(auto) std::__do_visit(_Visitor&&, _Variants&& ...) [with _Result_type = __detail::__variant::__variant_idx_cookie; _Visitor = __detail::__variant::_Move_ctor_base, allocator > >::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base, std::allocator > >&&)::; _Variants = {variant<{anonymous}::SdcGraphNode*, __cxx11::basic_string, allocator > >}]' at /usr/include/c++/15.2.0/variant:1892:5, inlined from 'constexpr void std::__detail::__variant::__raw_idx_visit(_Visitor&&, _Variants&& ...) [with _Visitor = _Move_ctor_base, std::allocator > >::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base, std::allocator > >&&)::; _Variants = {std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >}]' at /usr/include/c++/15.2.0/variant:187:44, inlined from 'std::__detail::__variant::_Move_ctor_base<, _Types>::_Move_ctor_base(std::__detail::__variant::_Move_ctor_base<, _Types>&&) [with bool = false; _Types = {{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator >}]' at /usr/include/c++/15.2.0/variant:622:28, inlined from 'std::__detail::__variant::_Copy_assign_base<, _Types>::_Copy_assign_base(std::__detail::__variant::_Copy_assign_base<, _Types>&&) [with bool = false; _Types = {{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator >}]' at /usr/include/c++/15.2.0/variant:687:7, inlined from 'std::__detail::__variant::_Move_assign_base<, _Types>::_Move_assign_base(std::__detail::__variant::_Move_assign_base<, _Types>&&) [with bool = false; _Types = {{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator >}]' at /usr/include/c++/15.2.0/variant:741:7, inlined from 'std::__detail::__variant::_Variant_base<_Types>::_Variant_base(std::__detail::__variant::_Variant_base<_Types>&&) [with _Types = {{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator >}]' at /usr/include/c++/15.2.0/variant:772:7, inlined from 'std::variant<_Types>::variant(std::variant<_Types>&&) [with _Types = {{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator >}]' at /usr/include/c++/15.2.0/variant:1487:7, inlined from 'void std::__new_allocator<_Tp>::construct(_Up*, _Args&& ...) [with _Up = std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >; _Args = {std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >}; _Tp = std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >]' at /usr/include/c++/15.2.0/bits/new_allocator.h:191:4, inlined from 'static void std::allocator_traits >::construct(allocator_type&, _Up*, _Args&& ...) [with _Up = std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >; _Args = {std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >}; _Tp = std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >]' at /usr/include/c++/15.2.0/bits/alloc_traits.h:674:17, inlined from 'std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::emplace_back(_Args&& ...) [with _Args = {std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >}; _Tp = std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >; _Alloc = std::allocator, std::allocator > > >]' at /usr/include/c++/15.2.0/bits/vector.tcc:117:30, inlined from 'void std::vector<_Tp, _Alloc>::push_back(value_type&&) [with _Tp = std::variant<{anonymous}::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >; _Alloc = std::allocator, std::allocator > > >]' at /usr/include/c++/15.2.0/bits/stl_vector.h:1434:21, inlined from 'void {anonymous}::SdcGraphNode::addChild({anonymous}::SdcGraphNode*)' at passes/cmds/sdc/sdc.cc:406:21, inlined from 'std::vector<{anonymous}::SdcGraphNode> {anonymous}::build_graph(const std::vector > >&)' at passes/cmds/sdc/sdc.cc:493:22, inlined from 'void {anonymous}::inspect_globals(Tcl_Interp*, bool)' at passes/cmds/sdc/sdc.cc:528:57, inlined from 'virtual void {anonymous}::SdcPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/cmds/sdc/sdc.cc:789:18: /usr/include/c++/15.2.0/bits/basic_string.h:282:17: warning: '*(const std::__cxx11::basic_string, std::allocator >*)((char*)& + offsetof(std::value_type, std::variant<::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::.std::__detail::__variant::_Variant_base<::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::.std::__detail::__variant::_Move_assign_base::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::.std::__detail::__variant::_Copy_assign_base::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::.std::__detail::__variant::_Move_ctor_base::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::.std::__detail::__variant::_Copy_ctor_base::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::.std::__detail::__variant::_Variant_storage::SdcGraphNode*, std::__cxx11::basic_string, std::allocator > >::_M_u)).std::__cxx11::basic_string::_M_string_length' may be used uninitialized [-Wmaybe-uninitialized] 282 | if (_M_string_length > _S_local_capacity) | ^~~~~~~~~~~~~~~~ passes/cmds/sdc/sdc.cc: In member function 'virtual void {anonymous}::SdcPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/cmds/sdc/sdc.cc:406:36: note: '' declared here 406 | children.push_back(child); | ^~~~~ [ 45%] Building passes/opt/opt_muxtree.o [ 45%] Building passes/opt/opt_reduce.o [ 46%] Building passes/opt/opt_dff.o [ 46%] Building passes/opt/opt_share.o [ 46%] Building passes/opt/opt_clean.o [ 47%] Building passes/opt/opt_expr.o [ 47%] Building passes/opt/opt_hier.o [ 47%] Building passes/opt/share.o [ 47%] Building passes/opt/wreduce.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from passes/fsm/fsm_opt.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:480: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 48%] Building passes/opt/opt_demorgan.o passes/opt/opt_merge.cc: In member function '{anonymous}::FoundDuplicates {anonymous}::OptMergeThreadWorker::find_duplicate_cells(int, const {anonymous}::Shards&) const': passes/opt/opt_merge.cc:330:65: warning: redundant move in initialization [-Wredundant-move] 330 | std::vector bucket = std::move(buckets[index]); | ~~~~~~~~~^~~~~~~~~~~~~~~~ passes/opt/opt_merge.cc:330:65: note: remove 'std::move' call [ 48%] Building passes/opt/rmports.o [ 48%] Building passes/opt/opt_lut.o [ 48%] Building passes/opt/opt_lut_ins.o [ 49%] Building passes/opt/opt_ffinv.o [ 49%] Building passes/opt/pmux2shiftx.o [ 49%] Building passes/opt/muxpack.o [ 49%] Building passes/opt/opt_balance_tree.o [ 49%] Building passes/opt/peepopt_pm.h [ 49%] Building passes/pmgen/test_pmgen_pm.h [ 49%] Building techlibs/ice40/ice40_dsp_pm.h [ 49%] Building techlibs/xilinx/xilinx_srl_pm.h [ 50%] Building passes/proc/proc.o [ 51%] Building passes/proc/proc_prune.o [ 51%] Building passes/proc/proc_clean.o [ 51%] Building passes/proc/proc_rmdead.o [ 51%] Building passes/proc/proc_init.o [ 52%] Building passes/proc/proc_arst.o [ 52%] Building passes/proc/proc_rom.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/hierarchy/hierarchy.cc:21: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/array:45, from ./kernel/yosys_common.h:23, from ./kernel/yosys.h:40, from passes/opt/opt_lut_ins.cc:20: In function '_OutIter std::__copy_move_a2(_InIter, _Sent, _OutIter) [with bool _IsMove = false; _InIter = const Yosys::RTLIL::SigBit*; _Sent = const Yosys::RTLIL::SigBit*; _OutIter = Yosys::RTLIL::SigBit*]', inlined from '_OI std::__copy_move_a1(_II, _II, _OI) [with bool _IsMove = false; _II = const Yosys::RTLIL::SigBit*; _OI = Yosys::RTLIL::SigBit*]' at /usr/include/c++/15.2.0/bits/stl_algobase.h:492:42, inlined from '_OI std::__copy_move_a(_II, _II, _OI) [with bool _IsMove = false; _II = const Yosys::RTLIL::SigBit*; _OI = Yosys::RTLIL::SigBit*]' at /usr/include/c++/15.2.0/bits/stl_algobase.h:500:31, inlined from '_OI std::copy(_II, _II, _OI) [with _II = const Yosys::RTLIL::SigBit*; _OI = Yosys::RTLIL::SigBit*]' at /usr/include/c++/15.2.0/bits/stl_algobase.h:642:7, inlined from 'void std::vector<_Tp, _Alloc>::_M_assign_aux(_ForwardIterator, _ForwardIterator, std::forward_iterator_tag) [with _ForwardIterator = const Yosys::RTLIL::SigBit*; _Tp = Yosys::RTLIL::SigBit; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/vector.tcc:343:19: /usr/include/c++/15.2.0/bits/stl_algobase.h:426:32: warning: argument 1 null where non-null expected because argument 3 is nonzero [-Wnonnull] 426 | __builtin_memmove(_GLIBCXX_TO_ADDR(__result), | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~ 427 | _GLIBCXX_TO_ADDR(__first), | ~~~~~~~~~~~~~~~~~~~~~~~~~~ 428 | __n * sizeof(*__first)); | ~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/c++/15.2.0/bits/stl_algobase.h:426:32: note: in a call to built-in function 'void* __builtin_memmove(void*, const void*, long unsigned int)' [ 52%] Building passes/proc/proc_mux.o [ 52%] Building passes/proc/proc_dlatch.o In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Wire* const&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Wire*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Wire* const&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Wire*; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Wire*; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 53%] Building passes/proc/proc_dff.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/opt/opt_hier.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 53%] Building passes/proc/proc_memwr.o [ 53%] Building passes/sat/sat.o [ 54%] Building passes/sat/freduce.o [ 54%] Building passes/sat/eval.o [ 54%] Building passes/sat/sim.o [ 54%] Building passes/sat/miter.o [ 55%] Building passes/sat/expose.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/opt/opt_merge.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 55%] Building passes/sat/assertpmux.o [ 55%] Building passes/sat/clk2fflogic.o [ 55%] Building passes/sat/async2sync.o [ 56%] Building passes/sat/formalff.o [ 56%] Building passes/sat/supercover.o [ 56%] Building passes/sat/fmcombine.o In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::UsageData::refine_tie_togethers(const Yosys::hashlib::dict&)' at passes/opt/opt_hier.cc:272:30, inlined from 'void {anonymous}::UsageData::refine(Yosys::RTLIL::Cell*, {anonymous}::ModuleIndex&)' at passes/opt/opt_hier.cc:310:23, inlined from 'virtual void {anonymous}::OptHierPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/opt/opt_hier.cc:453:39: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'virtual void {anonymous}::OptHierPass::execute(std::vector >, Yosys::RTLIL::Design*)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::UsageData::refine_tie_togethers(const Yosys::hashlib::dict&)' at passes/opt/opt_hier.cc:272:30, inlined from 'void {anonymous}::UsageData::refine(Yosys::RTLIL::Cell*, {anonymous}::ModuleIndex&)' at passes/opt/opt_hier.cc:310:23, inlined from 'virtual void {anonymous}::OptHierPass::execute(std::vector >, Yosys::RTLIL::Design*)' at passes/opt/opt_hier.cc:453:39: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'virtual void {anonymous}::OptHierPass::execute(std::vector >, Yosys::RTLIL::Design*)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from passes/fsm/fsm_extract.cc:25: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)' at passes/fsm/fsm_extract.cc:412:96: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In function 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:480: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)' at passes/fsm/fsm_extract.cc:412:96: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In function 'void {anonymous}::extract_fsm(Yosys::RTLIL::Wire*)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/opt/muxpack.cc:21: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::pair<_T1, _T2>::pair(std::pair<_T1, _T2>&&) [with _T1 = Yosys::RTLIL::SigSpec; _T2 = std::vector]' at /usr/include/c++/15.2.0/bits/stl_pair.h:313:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = std::pair >; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = std::pair >]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::pair > >,std::pair > >::first.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::pair<_T1, _T2>::pair(std::pair<_T1, _T2>&&) [with _T1 = Yosys::RTLIL::SigSpec; _T2 = std::vector]' at /usr/include/c++/15.2.0/bits/stl_pair.h:313:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = std::pair >; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = std::pair >]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::pair > >,std::pair > >::first.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair >; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 56%] Building passes/sat/mutate.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from kernel/rtlil.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 57%] Building passes/sat/cutpoint.o [ 57%] Building passes/sat/fminit.o [ 57%] Building passes/sat/recover_names.o [ 58%] Building passes/sat/qbfsat.o [ 58%] Building passes/sat/synthprop.o [ 58%] Building passes/techmap/techmap.o [ 58%] Building passes/techmap/simplemap.o [ 59%] Building passes/techmap/dfflibmap.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/opt/pmux2shiftx.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::pair<_T1, _T2>::pair(std::pair<_T1, _T2>&&) [with _T1 = Yosys::RTLIL::SigSpec; _T2 = Yosys::RTLIL::Const]' at /usr/include/c++/15.2.0/bits/stl_pair.h:313:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = std::pair; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = std::pair]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::pair,std::pair::first.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::pair<_T1, _T2>::pair(std::pair<_T1, _T2>&&) [with _T1 = Yosys::RTLIL::SigSpec; _T2 = Yosys::RTLIL::Const]' at /usr/include/c++/15.2.0/bits/stl_pair.h:313:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::SigBit&; _U2 = std::pair; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::SigBit; _T2 = std::pair]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::pair,std::pair::first.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::SigBit; T = std::pair; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 59%] Building passes/techmap/maccmap.o [ 59%] Building passes/techmap/booth.o [ 59%] Building passes/techmap/libparse.o [ 60%] Building passes/techmap/libcache.o [ 60%] Building passes/techmap/abc.o [ 60%] Building passes/techmap/abc9.o [ 60%] Building passes/techmap/abc9_exe.o [ 61%] Building passes/techmap/abc9_ops.o [ 61%] Building passes/techmap/abc_new.o [ 61%] Building passes/techmap/iopadmap.o [ 62%] Building passes/techmap/clkbufmap.o [ 62%] Building passes/techmap/hilomap.o [ 62%] Building passes/techmap/extract.o [ 62%] Building passes/techmap/extract_fa.o [ 63%] Building passes/techmap/extract_counter.o [ 63%] Building passes/techmap/extract_reduce.o [ 63%] Building passes/techmap/alumacc.o [ 63%] Building passes/techmap/dffinit.o [ 64%] Building passes/techmap/pmuxtree.o [ 64%] Building passes/techmap/bmuxmap.o [ 64%] Building passes/techmap/demuxmap.o [ 65%] Building passes/techmap/bwmuxmap.o [ 65%] Building passes/techmap/muxcover.o [ 65%] Building passes/techmap/aigmap.o [ 65%] Building passes/techmap/tribuf.o [ 66%] Building passes/techmap/lut2mux.o [ 66%] Building passes/techmap/lut2bmux.o [ 66%] Building passes/techmap/nlutmap.o [ 66%] Building passes/techmap/shregmap.o [ 67%] Building passes/techmap/deminout.o [ 67%] Building passes/techmap/insbuf.o [ 67%] Building passes/techmap/bufnorm.o [ 67%] Building passes/techmap/attrmvcp.o [ 68%] Building passes/techmap/attrmap.o [ 68%] Building passes/techmap/zinit.o [ 68%] Building passes/techmap/dfflegalize.o [ 69%] Building passes/techmap/dffunmap.o [ 69%] Building passes/techmap/flowmap.o [ 69%] Building passes/techmap/extractinv.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/yosys.h:40, from passes/techmap/dfflibmap.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 69%] Building passes/techmap/cellmatch.o [ 70%] Building passes/techmap/clockgate.o [ 70%] Building passes/techmap/constmap.o [ 70%] Building passes/tests/test_autotb.o [ 70%] Building passes/tests/test_cell.o [ 71%] Building passes/tests/test_abcloop.o [ 71%] Building passes/tests/raise_error.o [ 71%] Building backends/aiger/aiger.o [ 72%] Building backends/aiger/xaiger.o [ 72%] Building backends/aiger2/aiger.o [ 72%] Building backends/blif/blif.o [ 72%] Building backends/btor/btor.o [ 73%] Building backends/cxxrtl/cxxrtl_backend.o [ 73%] Building backends/edif/edif.o [ 73%] Building backends/firrtl/firrtl.o [ 73%] Building backends/functional/cxx.o [ 74%] Building backends/functional/smtlib.o [ 74%] Building backends/functional/smtlib_rosette.o [ 74%] Building backends/functional/test_generic.o [ 74%] Building backends/intersynth/intersynth.o [ 75%] Building backends/jny/jny.o [ 75%] Building backends/json/json.o [ 75%] Building backends/rtlil/rtlil_backend.o [ 76%] Building backends/simplec/simplec.o [ 76%] Building backends/smt2/smt2.o [ 76%] Building backends/smv/smv.o [ 76%] Building backends/spice/spice.o [ 77%] Building backends/table/table.o [ 77%] Building backends/verilog/verilog_backend.o [ 77%] Building techlibs/achronix/synth_achronix.o [ 77%] Building techlibs/anlogic/synth_anlogic.o [ 78%] Building techlibs/anlogic/anlogic_eqn.o [ 78%] Building techlibs/anlogic/anlogic_fixcarry.o [ 78%] Building techlibs/common/synth.o [ 78%] Building techlibs/common/prep.o [ 79%] Building techlibs/common/opensta.o [ 79%] Building techlibs/common/sdc_expand.o [ 79%] Building techlibs/coolrunner2/synth_coolrunner2.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23, from backends/jny/jny.cc:20: In destructor 'std::_Vector_base<_Tp, _Alloc>::~_Vector_base() [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::vector<_Tp, _Alloc>::~vector() [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:805:7, inlined from 'Yosys::RTLIL::SigChunk::~SigChunk()' at ./kernel/rtlil.h:1283:15, inlined from 'void Yosys::RTLIL::SigSpec::destroy()' at ./kernel/rtlil.h:1448:20, inlined from 'void Yosys::RTLIL::SigSpec::destroy()' at ./kernel/rtlil.h:1446:7, inlined from 'Yosys::RTLIL::SigSpec::~SigSpec()' at ./kernel/rtlil.h:1485:10, inlined from 'std::pair::~pair()' at /usr/include/c++/15.2.0/bits/stl_pair.h:302:12, inlined from 'void {anonymous}::JnyWriter::write_cell_ports(Yosys::RTLIL::Cell*, uint64_t)' at backends/jny/jny.cc:297:9: /usr/include/c++/15.2.0/bits/stl_vector.h:376:49: warning: '*(std::_Vector_base >*)((char*)&con + offsetof(std::pair,std::pair::second.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_M_impl.std::_Vector_base >::_Vector_impl::std::_Vector_base >::_Vector_impl_data.std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 376 | _M_impl._M_end_of_storage - _M_impl._M_start); | ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ backends/jny/jny.cc: In member function 'void {anonymous}::JnyWriter::write_cell_ports(Yosys::RTLIL::Cell*, uint64_t)': backends/jny/jny.cc:278:19: note: '*(std::_Vector_base >*)((char*)&con + offsetof(std::pair,std::pair::second.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_M_impl.std::_Vector_base >::_Vector_impl::std::_Vector_base >::_Vector_impl_data.std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' was declared here 278 | for (auto con : port_cell->connections()) { | ^~~ backends/jny/jny.cc:290:13: warning: '*(Yosys::RTLIL::SigChunk*)((char*)&con + offsetof(std::pair,std::pair::second.Yosys::RTLIL::SigSpec::)).Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 290 | if (con.second.size() == 1) | ^~ backends/jny/jny.cc:278:19: note: '*(Yosys::RTLIL::SigChunk*)((char*)&con + offsetof(std::pair,std::pair::second.Yosys::RTLIL::SigSpec::)).Yosys::RTLIL::SigChunk::width' was declared here 278 | for (auto con : port_cell->connections()) { | ^~~ [ 80%] Building techlibs/coolrunner2/coolrunner2_sop.o [ 80%] Building techlibs/coolrunner2/coolrunner2_fixup.o [ 80%] Building techlibs/easic/synth_easic.o [ 80%] Building techlibs/efinix/synth_efinix.o [ 81%] Building techlibs/efinix/efinix_fixcarry.o [ 81%] Building techlibs/fabulous/synth_fabulous.o [ 81%] Building techlibs/gatemate/synth_gatemate.o [ 81%] Building techlibs/gatemate/gatemate_foldinv.o In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24, from passes/techmap/abc9_ops.cc:21: In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'void {anonymous}::prep_delays(Yosys::RTLIL::Design*, bool)' at passes/techmap/abc9_ops.cc:681:26: ./kernel/rtlil.h:1596:86: warning: 'rhs.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1596 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ passes/techmap/abc9_ops.cc: In function 'void {anonymous}::prep_delays(Yosys::RTLIL::Design*, bool)': passes/techmap/abc9_ops.cc:680:30: note: 'rhs' declared here 680 | auto rhs = cell->getPort(i.first.name); | ^~~ [ 82%] Building techlibs/gowin/synth_gowin.o [ 82%] Building techlibs/greenpak4/synth_greenpak4.o [ 82%] Building techlibs/greenpak4/greenpak4_dffinv.o [ 83%] Building techlibs/ice40/synth_ice40.o [ 83%] Building techlibs/ice40/ice40_braminit.o In file included from ./kernel/yosys.h:43, from techlibs/anlogic/anlogic_fixcarry.cc:20: In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'int Yosys::GetSize(const T&) [with T = RTLIL::SigSpec]' at ./kernel/yosys_common.h:267:65, inlined from 'void {anonymous}::fix_carry_chain(Yosys::RTLIL::Module*)' at techlibs/anlogic/anlogic_fixcarry.cc:49:16: ./kernel/rtlil.h:1596:86: warning: 'o.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1596 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ techlibs/anlogic/anlogic_fixcarry.cc: In function 'void {anonymous}::fix_carry_chain(Yosys::RTLIL::Module*)': techlibs/anlogic/anlogic_fixcarry.cc:48:41: note: 'o' declared here 48 | SigSpec o = cell->getPort(ID(o)); | ^ [ 83%] Building techlibs/ice40/ice40_opt.o [ 83%] Building techlibs/ice40/ice40_dsp.o [ 83%] Building techlibs/ice40/ice40_wrapcarry_pm.h [ 84%] Building techlibs/intel/synth_intel.o [ 84%] Building techlibs/intel_alm/synth_intel_alm.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)' at passes/techmap/abc9_ops.cc:844:53: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In function 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)' at passes/techmap/abc9_ops.cc:844:53: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In function 'void {anonymous}::prep_xaiger(Yosys::RTLIL::Module*, bool)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 84%] Building techlibs/lattice/synth_lattice.o [ 85%] Building techlibs/lattice/lattice_gsr.o [ 85%] Building techlibs/microchip/synth_microchip.o [ 85%] Building techlibs/microchip/microchip_dffopt.o [ 85%] Building techlibs/microchip/microchip_dsp_pm.h [ 85%] Building techlibs/microchip/microchip_dsp_CREG_pm.h [ 85%] Building techlibs/microchip/microchip_dsp_cascade_pm.h [ 86%] Building techlibs/nanoxplore/synth_nanoxplore.o [ 86%] Building techlibs/nanoxplore/nx_carry.o [ 86%] Building techlibs/quicklogic/synth_quicklogic.o [ 87%] Building techlibs/quicklogic/ql_bram_merge.o In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/register.h:23, from passes/techmap/abc.cc:44: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:586:41, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 6; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<6, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<7, Yosys::RTLIL::SigSpec>::.std::_Head_base<7, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/register.h:24: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head>&&) [with long unsigned int _Idx = 7; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:586:41, inlined from 'constexpr std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 6; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<6, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<7, Yosys::RTLIL::SigSpec>::.std::_Head_base<7, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<5, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 5; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 4; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<4, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<5, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<5, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<3, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 3; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 2; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<2, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<3, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<3, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<1, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'std::_Head_base<_Idx, _Head, false>::_Head_base(std::_Head_base<_Idx, _Head, false>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/tuple:209:17, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 1; _Head = Yosys::RTLIL::SigSpec; _Tail = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::_Tuple_impl<_Idx, _Head, _Tail ...>::_Tuple_impl(std::_Tuple_impl<_Idx, _Head, _Tail ...>&&) [with long unsigned int _Idx = 0; _Head = bool; _Tail = {Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:324:7, inlined from 'std::tuple< >::tuple(std::tuple< >&&) [with _Elements = {bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec}]' at /usr/include/c++/15.2.0/tuple:1504:17, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = Yosys::RTLIL::Cell* const&; _U2 = std::tuple; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::Cell*; _T2 = std::tuple]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(std::tuple,std::tuple::.std::_Tuple_impl<0, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Tuple_impl<1, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec, bool, Yosys::RTLIL::SigSpec>::.std::_Head_base<1, Yosys::RTLIL::SigSpec, false>::_M_head_impl.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::Cell*; T = std::tuple; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ [ 87%] Building techlibs/quicklogic/ql_bram_types.o In file included from ./kernel/yosys.h:43, from techlibs/gatemate/gatemate_foldinv.cc:21: In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'int Yosys::GetSize(const T&) [with T = RTLIL::SigSpec]' at ./kernel/yosys_common.h:267:65, inlined from 'void {anonymous}::FoldInvWorker::fold_input_inverters()' at techlibs/gatemate/gatemate_foldinv.cc:109:28: ./kernel/rtlil.h:1596:86: warning: 'sig.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1596 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ techlibs/gatemate/gatemate_foldinv.cc: In member function 'void {anonymous}::FoldInvWorker::fold_input_inverters()': techlibs/gatemate/gatemate_foldinv.cc:108:22: note: 'sig' declared here 108 | auto sig = cell->getPort(ipin.first); | ^~~ [ 87%] Building techlibs/quicklogic/ql_dsp_simd.o [ 87%] Building techlibs/quicklogic/ql_dsp_io_regs.o [ 88%] Building techlibs/quicklogic/ql_ioff.o [ 88%] Building techlibs/quicklogic/ql_dsp_macc_pm.h [ 88%] Building techlibs/sf2/synth_sf2.o In member function 'int Yosys::RTLIL::SigSpec::size() const', inlined from 'int Yosys::GetSize(const T&) [with T = RTLIL::SigSpec]' at ./kernel/yosys_common.h:267:65, inlined from 'void {anonymous}::FoldInvWorker::fold_output_inverters()' at techlibs/gatemate/gatemate_foldinv.cc:147:24: ./kernel/rtlil.h:1596:86: warning: 'o_sig.Yosys::RTLIL::SigSpec::.Yosys::RTLIL::SigSpec::::chunk_.Yosys::RTLIL::SigChunk::width' may be used uninitialized [-Wmaybe-uninitialized] 1596 | inline int size() const { return rep_ == CHUNK ? chunk_.width : GetSize(bits_); } | ^ techlibs/gatemate/gatemate_foldinv.cc: In member function 'void {anonymous}::FoldInvWorker::fold_output_inverters()': techlibs/gatemate/gatemate_foldinv.cc:146:18: note: 'o_sig' declared here 146 | auto o_sig = cell->getPort(ID::O); | ^~~~~ [ 88%] Building techlibs/xilinx/synth_xilinx.o [ 89%] Building techlibs/xilinx/xilinx_dffopt.o [ 89%] Building techlibs/xilinx/xilinx_dsp_pm.h [ 89%] Building techlibs/xilinx/xilinx_dsp48a_pm.h [ 89%] Building techlibs/xilinx/xilinx_dsp_CREG_pm.h [ 89%] Building techlibs/xilinx/xilinx_dsp_cascade_pm.h [ 89%] Building techlibs/xilinx/xilinx_srl.o [ 99%] Building yosys-config [ 99%] Building passes/techmap/filterlib.o [ 99%] Building yosys-smtbmc [ 99%] Building yosys-witness [ 99%] Building share/include/kernel/binding.h [ 99%] Building share/include/kernel/bitpattern.h [ 99%] Building share/include/kernel/cellaigs.h [ 99%] Building share/include/kernel/celledges.h [ 99%] Building share/include/kernel/celltypes.h [ 99%] Building share/include/kernel/consteval.h [ 99%] Building share/include/kernel/constids.inc [ 99%] Building share/include/kernel/cost.h [ 99%] Building share/include/kernel/drivertools.h [ 99%] Building share/include/kernel/ff.h [ 99%] Building share/include/kernel/ffinit.h [ 99%] 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file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/log.h:23, from techlibs/quicklogic/ql_dsp_simd.cc:19: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)' at techlibs/quicklogic/ql_dsp_simd.cc:269:27: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In function '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from ./kernel/yosys.h:43, from ./kernel/log.h:480: In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23, inlined from '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)' at techlibs/quicklogic/ql_dsp_simd.cc:269:27: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In function '{anonymous}::QlDspSimdPass::DspConfig {anonymous}::QlDspSimdPass::getDspConfig(Yosys::RTLIL::Cell*, const std::vector >&)': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23, from backends/cxxrtl/cxxrtl_backend.cc:20: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from '{anonymous}::WireType::WireType({anonymous}::WireType&&)' at backends/cxxrtl/cxxrtl_backend.cc:649:8, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::Wire* const&; _U2 = {anonymous}::WireType; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = const Yosys::RTLIL::Wire*; _T2 = {anonymous}::WireType]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(::WireType, ::WireType::sig_subst.Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from '{anonymous}::WireType::WireType({anonymous}::WireType&&)' at backends/cxxrtl/cxxrtl_backend.cc:649:8, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::Wire* const&; _U2 = {anonymous}::WireType; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = const Yosys::RTLIL::Wire*; _T2 = {anonymous}::WireType]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(::WireType, ::WireType::sig_subst.Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = const Yosys::RTLIL::Wire*; T = {anonymous}::WireType; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc: In function 'void pyosys::pybind11_init_libyosys(pybind11::module_&)': /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:563:90: warning: 'bool Yosys::RTLIL::IdString::in(const Yosys::hashlib::pool&) const' is deprecated [-Wdeprecated-declarations] In file included from ./kernel/binding.h:23, from /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:21: ./kernel/rtlil.h:665:13: note: declared here 665 | inline bool RTLIL::IdString::in(const pool &rhs) const { return rhs.count(*this) != 0; } | ^~~~~ In file included from /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:30: ./pyosys/hashlib.h: In instantiation of 'void pybind11::hashlib::bind_idict(pybind11::module&, const char*) [with C = Yosys::hashlib::idict; K = Yosys::RTLIL::IdString; pybind11::module = pybind11::module_]': pyosys/wrappers.inc.cc:172:52: required from here 172 | py::hashlib::bind_idict, IdString>(m, "IdstringIdict"); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ./pyosys/hashlib.h:484:40: warning: unused parameter '_' [-Wunused-parameter] 484 | .def("values", [](args _){ | ~~~~~^ ./pyosys/hashlib.h:487:39: warning: unused parameter '_' [-Wunused-parameter] 487 | .def("items", [](args _){ | ~~~~~^ ./pyosys/hashlib.h:523:42: warning: unused parameter '_' [-Wunused-parameter] 523 | cls.def(mutator, [](args _) { | ~~~~~^ [ 99%] Building yosys-filterlib kernel/register.cc: In constructor 'Yosys::CellHelpMessages::CellHelpMessages()': kernel/register.cc:742:9: note: variable tracking size limit exceeded with '-fvar-tracking-assignments', retrying without 742 | CellHelpMessages() { | ^~~~~~~~~~~~~~~~ In file included from /usr/include/c++/15.2.0/vector:68, from ./kernel/yosys_common.h:28, from ./kernel/rtlil.h:23: In constructor 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data::_Vector_impl_data(std::_Vector_base<_Tp, _Alloc>::_Vector_impl_data&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]', inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_impl::_Vector_impl(std::_Vector_base<_Tp, _Alloc>::_Vector_impl&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:161:68, inlined from 'std::_Vector_base<_Tp, _Alloc>::_Vector_base(std::_Vector_base<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:344:7, inlined from 'std::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>&&) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator]' at /usr/include/c++/15.2.0/bits/stl_vector.h:650:7, inlined from 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)' at ./kernel/rtlil.h:1283:15, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: /usr/include/c++/15.2.0/bits/stl_vector.h:113:33: warning: '*(std::_Vector_base >::_Vector_impl_data*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::) + 8).std::_Vector_base >::_Vector_impl_data::_M_end_of_storage' may be used uninitialized [-Wmaybe-uninitialized] 113 | _M_end_of_storage(__x._M_end_of_storage) | ~~~~^~~~~~~~~~~~~~~~~ In file included from ./kernel/yosys_common.h:158: ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In constructor 'Yosys::RTLIL::SigChunk::SigChunk(Yosys::RTLIL::SigChunk&&)', inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1465:57, inlined from 'Yosys::RTLIL::SigSpec::SigSpec(Yosys::RTLIL::SigSpec&&)' at ./kernel/rtlil.h:1463:2, inlined from 'constexpr std::pair<_T1, _T2>::pair(_U1&&, _U2&&) [with _U1 = const Yosys::RTLIL::IdString&; _U2 = Yosys::RTLIL::SigSpec; typename std::enable_if<(std::_PCC::_MoveConstructiblePair<_U1, _U2>() && std::_PCC::_ImplicitlyMoveConvertiblePair<_U1, _U2>()), bool>::type = true; _T1 = Yosys::RTLIL::IdString; _T2 = Yosys::RTLIL::SigSpec]' at /usr/include/c++/15.2.0/bits/stl_pair.h:902:35, inlined from 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]' at ./kernel/hashlib.h:822:23: ./kernel/rtlil.h:1283:15: warning: '((__vector(2) int*)((char*)& + offsetof(Yosys::RTLIL::SigSpec, Yosys::RTLIL::SigSpec::)))[4]' may be used uninitialized [-Wmaybe-uninitialized] 1283 | struct RTLIL::SigChunk | ^~~~~~~~ ./kernel/hashlib.h: In member function 'T& Yosys::hashlib::dict::operator[](const K&) [with K = Yosys::RTLIL::IdString; T = Yosys::RTLIL::SigSpec; OPS = Yosys::hashlib::hash_ops]': ./kernel/hashlib.h:822:60: note: '' declared here 822 | i = do_insert(std::pair(key, T()), hash); | ^~~ In file included from /usr/lib/python3.12/site-packages/pybind11/include/pybind11/attr.h:13, from /usr/lib/python3.12/site-packages/pybind11/include/pybind11/detail/class.h:12, from /usr/lib/python3.12/site-packages/pybind11/include/pybind11/pybind11.h:12, from /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:22: /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc: In function 'void pyosys::pybind11_init_libyosys(pybind11::module_&)': /usr/lib/python3.12/site-packages/pybind11/include/pybind11/detail/common.h:467:26: note: variable tracking size limit exceeded with '-fvar-tracking-assignments', retrying without 467 | void PYBIND11_CONCAT(pybind11_init_, name)(::pybind11::module_ \ | ^~~~~~~~~~~~~~ /usr/lib/python3.12/site-packages/pybind11/include/pybind11/detail/common.h:347:40: note: in definition of macro 'PYBIND11_CONCAT' 347 | #define PYBIND11_CONCAT(first, second) first##second | ^~~~~ /usr/lib/python3.12/site-packages/pybind11/include/pybind11/detail/common.h:512:5: note: in expansion of macro 'PYBIND11_MODULE_EXEC' 512 | PYBIND11_MODULE_EXEC(name, variable) | ^~~~~~~~~~~~~~~~~~~~ /home/buildozer/aports/testing/yosys/src/pyosys/wrappers_tpl.cc:168:9: note: in expansion of macro 'PYBIND11_MODULE' 168 | PYBIND11_MODULE(libyosys, m) { | ^~~~~~~~~~~~~~~ [100%] Building yosys [100%] Building libyosys.so Build successful. [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=/usr/bin/abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_ABC:=1 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] PYOSYS_USE_UV:=0 cd tests/arch/anlogic/ && bash run-test.sh cd tests/arch/ecp5/ && bash run-test.sh cd tests/arch/efinix/ && bash run-test.sh cd tests/arch/gatemate/ && bash run-test.sh cd tests/arch/gowin/ && bash run-test.sh cd tests/arch/ice40/ && bash run-test.sh cd tests/arch/intel_alm/ && bash run-test.sh cd tests/arch/machxo2/ && bash run-test.sh cd tests/arch/microchip/ && bash run-test.sh cd tests/arch/nanoxplore/ && bash run-test.sh cd tests/arch/nexus/ && bash run-test.sh cd tests/arch/quicklogic/pp3/ && bash run-test.sh cd tests/arch/quicklogic/qlf_k6n10f/ && bash run-test.sh cd tests/arch/xilinx/ && bash run-test.sh cd tests/bugpoint/ && bash run-test.sh cd tests/opt/ && bash run-test.sh cd tests/sat/ && bash run-test.sh cd tests/sdc/ && bash run-test.sh cd tests/sim/ && bash run-test.sh cd tests/svtypes/ && bash run-test.sh cd tests/techmap/ && bash run-test.sh cd tests/various/ && bash run-test.sh cd tests/rtlil/ && bash run-test.sh Generate FST for sim models cd tests/verilog/ && bash run-test.sh Test tb_adff cd tests/memories && bash run-test.sh "-A /usr/bin/abc" "" cd tests/aiger && bash run-test.sh "-A /usr/bin/abc" "" cd tests/alumacc && bash run-test.sh "-A /usr/bin/abc" "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memories' Checking and_.aag. cd tests/simple && bash run-test.sh "" Running basic.ys.. cd tests/simple_abc9 && bash run-test.sh "" + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + cd tests/hana && bash run-test.sh "" g++ + -Wall g++ -o -Wall /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c/home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/simple' cd tests/asicworld && bash run-test.sh "" + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall ls: *.sv: No such file or directory -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c cd tests/share && bash run-test.sh "" + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c FST info: dumpfile tb_adff.fst opened for output. + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c cd tests/opt_share && bash run-test.sh "" make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/hana' + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c tb/tb_adff.v:38: $finish called at 110 (1ns) + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c cd tests/fsm && bash run-test.sh "" + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/asicworld' + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c generating tests.. + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c Test tb_adffe generating tests.. + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c generating tests.. + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/simple_abc9' + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c FST info: dumpfile tb_adffe.fst opened for output. tb/tb_adffe.v:56: $finish called at 190 (1ns) Test tb_adlatch + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c FST info: dumpfile tb_adlatch.fst opened for output. + g++ -Wall -o /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata /home/buildozer/aports/testing/yosys/src/tests/tools/cmp_tbdata.c tb/tb_adlatch.v:68: $finish called at 250 (1ns) Test tb_aldff FST info: dumpfile tb_aldff.fst opened for output. tb/tb_aldff.v:71: $finish called at 270 (1ns) Test tb_aldffe FST info: dumpfile tb_aldffe.fst opened for output. tb/tb_aldffe.v:73: $finish called at 270 (1ns) Test tb_dff FST info: dumpfile tb_dff.fst opened for output. running tests.. tb/tb_dff.v:45: $finish called at 150 (1ns) Test tb_dffe cd tests/memlib && bash run-test.sh "" [0]FST info: dumpfile tb_dffe.fst opened for output. tb/tb_dffe.v:40: $finish called at 120 (1ns) Test tb_dffsr FST info: dumpfile tb_dffsr.fst opened for output. tb/tb_dffsr.v:67: $finish called at 250 (1ns) Test tb_dlatch PRNG seed: 1038392401929857850 FST info: dumpfile tb_dlatch.fst opened for output. tb/tb_dlatch.v:48: $finish called at 160 (1ns) Test tb_dlatchsr Checking and_to_bad_out.aag. FST info: dumpfile tb_dlatchsr.fst opened for output. tb/tb_dlatchsr.v:63: $finish called at 250 (1ns) [1]Test tb_sdff FST info: dumpfile tb_sdff.fst opened for output. tb/tb_sdff.v:46: $finish called at 150 (1ns) Test tb_sdffce running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/opt_share' [0][1]running tests.. FST info: dumpfile tb_sdffce.fst opened for output. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/fsm' [0]tb/tb_sdffce.v:77: $finish called at 300 (1ns) Test tb_sdffe FST info: dumpfile tb_sdffe.fst opened for output. tb/tb_sdffe.v:68: $finish called at 250 (1ns) [2][2]make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/memlib' Running macc_b_port_compat.ys.. [3]Checking buffer.aag. [4]Running macc_infer_n_unmap.ys.. [5][6]...passed tests in tests/alumacc cd tests/bram && bash run-test.sh "" Test: case_expr_extend -> ok Test: case_expr_query -> ok generating tests.. Checking cnt1.aag. Test: local_loop_var -> ok [1]Test: matching_end_labels -> ok [2][7]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. [8]Test: always01 -> ok [3]Test: always02 -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: aes_kexp128 -> ok Checking cnt1e.aag. [9]Test: code_hdl_models_arbiter -> ok [3][10]PRNG seed: 877642 cd tests/svinterfaces && bash run-test.sh "" Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: svinterface1 -> Test: code_hdl_models_GrayCounter -> ok cd tests/xprop && bash run-test.sh "" Test: lesser_size_cast -> ok [4]running tests.. make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bram' [11]Checking empty.aag. xprop PRNG seed: 2447149305 make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/xprop' [12]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Warning: The current network has no primary outputs. Some commands may not work correctly. Test: always03 -> ok [13]Test: implicit_ports -> ok Test: arrays02 -> ok Checking false.aag. [14]Test: t_async_small -> ok cd tests/select && bash run-test.sh "" Running boxes_equals_name.ys.. Running boxes_equals_operators.ys.. [15]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Test: firrtl_938 -> ok Running boxes_equals_pattern.ys.. Test: memwr_port_connection -> ok Running boxes_equals_wildcard.ys.. Checking halfadder.aag. [16]Running boxes_import.ys.. KTest: test_parse2synthtrans -> ok Warning: Selection "wb" did not match any module. ERROR: No top module found in source design. Expected error pattern 'No top module found in source design\.' found !!! Running boxes_no_equals.ys.. Test: implicit_en -> ok [17]Test: defvalue -> ok [4]Test: no_implicit_en -> ok Running boxes_no_equals_clean.ys.. Test: macro_arg_spaces -> ok Warning: Selection "wb" did not match any module. [18]Running boxes_setattr.ys.. cd tests/peepopt && bash run-test.sh "" Running muldiv_c.ys.. Running boxes_stack.ys.. Test: simple_sram_byte_en -> ok Checking inverter.aag. [19]Running internal_selects.ys.. Warning: Ignoring blackbox module bb. Warning: Ignoring boxed module wb. Warning: Ignoring boxed module bb. [20]Warning: Ignoring partially selected module wb. Warning: Ignoring partially selected module top. Test: wide_thru_priority -> ok cd tests/proc && bash run-test.sh "" Running list_mod.ys.. Running bug2619.ys.. Running mod-attribute.ys.. Running bug2656.ys.. [21]Running no_warn_assert.ys.. Warning: wire '\q1' is assigned in a block at < ok Running no_warn_prefixed_arg_memb.ys.. Running bug2962.ys.. [22]Test: shared_ports -> ok Running bug4712.ys.. Running no_warn_prefixed_empty_select_arg.ys.. K[5]Warning: Async reset value `\a_r' is not constant! [23]Running bug5572.ys.. Test: unnamed_block_decl -> ok [6]Warning: The new network has no primary inputs. It is recommended Running unset.ys.. to add a dummy PI to make sure all commands work correctly. ERROR: Selection '\foo' does not exist! Expected error pattern 'Selection '\\foo' does not exist!' found !!! Running unset2.ys.. Running bug_1268.ys.. Test: t_sync_big -> ok [24]ERROR: Selection @foo is not defined! Expected error pattern 'Selection @foo is not defined!' found !!! cd tests/blif && bash run-test.sh "" Running bug2729.ys.. Running warn_empty_select_arg.ys.. Checking notcnt1e.aag. Running case_attr.ys.. Warning: Selection "foo" did not match any module. Warning: Selection "bar" did not match any object. ...passed tests in tests/select Test: wide_read_async -> ok Test: arrays01 -> ok [25][5]Running bug3374.ys.. Test: wide_all -> ok cd tests/arch && bash run-test.sh "" Running syntax check on arch sim models Test ../../techlibs/achronix/speedster22i/cells_sim.v ->Test: test_parser -> ok ERROR: Syntax error in line 1! Expected error pattern 'Syntax error in line 1!' found !!! ok Running bug3385.ys.. Test ../../techlibs/anlogic/cells_sim.v ->Running clean_undef_case.ys.. ok Test ../../techlibs/coolrunner2/cells_sim.v ->[26]Passed memory_bram test 00_02. ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals. Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!! ok Test ../../techlibs/efinix/cells_sim.v ->Running gatesi.ys.. Running proc_dff.ys.. ok Test ../../techlibs/gatemate/cells_sim.v ->Passed memory_bram test 00_01. Test: wide_write -> ok Test: wide_read_sync -> ok Warning: Complex async reset for dff `\q'. [27]...passed tests in tests/blif Test: trans_sp -> ok [6] ok Test ../../techlibs/gowin/cells_sim.v ->Test: read_arst -> ok Checking or_.aag. Test: trans_sdp -> ok Test: wide_read_mixed -> ok K ok Test: trans_addr_enable -> ok Running proc_rom.ys.. [7]Test ../../techlibs/greenpak4/cells_sim.v -> ok Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->[28]Warning: wire '\d' is assigned in a block at < ok Test: read_two_mux -> ok [8]svinterface1_tb.v:50: $finish called at 420000 (10ps) Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: wide_read_trans -> ok ok Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->svinterface1_tb.v:50: $finish called at 420000 (10ps) ok Test: svinterface_at_top -> ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. Warning: wire '\d' is assigned in a block at < ok [29] ok Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. xprop_not_3s_5: ok xprop_not_3s_5: ok Warning: wire '\d' is assigned in a block at <[30]Checking symbols.aag. ok Test ../../techlibs/intel/cycloneive/cells_sim.v ->Warning: wire '\d' is assigned in a block at <Test: issue00710 -> ok ok Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok Test ../../techlibs/intel_alm/cyclonev/cells_sim.v ->Running rmdead.ys.. [31] ok Test ../../techlibs/microchip/cells_sim.v ->Test: attrib01_module -> ok ok K[9]Test ../../techlibs/nanoxplore/cells_sim.v ->...passed tests in tests/proc ok Test ../../techlibs/quicklogic/common/cells_sim.v -> ok Test ../../techlibs/quicklogic/pp3/cells_sim.v ->Test: attrib02_port_decl -> ok [32] ok Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v -> ok Test ../../techlibs/sf2/cells_sim.v ->Test: code_hdl_models_clk_div_45 -> ok ok [7]Checking toggle-re.aag. Test ../../techlibs/xilinx/cells_sim.v ->[33]Test: code_hdl_models_d_ff_gates -> ok ok Test ../../techlibs/common/simcells.v ->Test: t_sync_big_sdp -> ok xprop_neg_3s_5: ok xprop_neg_3s_5: ok cd tests/rpc && bash run-test.sh "" Running exec.ys.. ok Test ../../techlibs/common/simlib.v ->[34] ok ...passed tests in tests/arch Checking toggle.aag. Test: test_simulation_buffer -> ok [35][36]Test: arrays03 -> ok Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Test: t_sync_small -> ok Test: aes_kexp128 -> ok [37]Test: always01 -> ok [8]Checking true.aag. Test: amber23_sram_byte_en -> ok ...passed tests in tests/rpc Test: code_hdl_models_d_latch_gates -> ok Test: always02 -> ok Passed memory_bram test 00_04. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [38]Test: attrib03_parameter -> ok Warning: The new network has no primary inputs. It is recommended Test: test_simulation_and -> ok to add a dummy PI to make sure all commands work correctly. Checking and_.aig. xprop_and_1u1_1: ok xprop_and_1u1_1: ok [10][39][40]Test: always03 -> ok xprop_and_1s1_2: ok xprop_and_1s1_2: ok Test: code_hdl_models_decoder_2to4_gates -> ok Passed memory_bram test 00_03. [9]Checking and_to_bad_out.aig. [41]Test: attrib04_net_var -> ok [11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! xprop_and_2u2_2: ok xprop_and_2u2_2: ok [42]Checking buffer.aig. [43]Test: code_hdl_models_decoder_using_assign -> ok [12]Test: t_sync_small_block -> ok [44]Test: test_simulation_always -> ok cd tests/memfile && bash run-test.sh "" Running from the parent directory with content1.dat svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) Running from the parent directory with temp/content2.dat svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) Test: arraycells -> ok ERROR! [45]Test: load_and_derive ->Checking cnt1.aig. Running from the parent directory with memfile/temp/content2.dat Passed memory_bram test 01_00. ok Test: resolve_types ->Test: test_simulation_nand -> ok [10]Test: test_simulation_nor -> ok [11][46]Test: code_hdl_models_decoder_using_case -> ok cd tests/fmt && bash run-test.sh "" + ../../yosys -p 'read_verilog initial_display.v' + awk '/<<>>/,/<<>>/ {print $0}' KRunning from the same directory with content1.dat ok Test: positional_args ->Test: t_sync_small_block_attr -> ok Passed memory_bram test 01_02. cd tests/cxxrtl && bash run-test.sh "" [47]+ run_subtest value + local subtest=value + shift + g++ -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++ Test: t_init_lut_zeros_zero -> ok [13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! ok ...passed tests in tests/svinterfaces [12]Running from the same directory with temp/content2.dat + iverilog -o iverilog-initial_display initial_display.v Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. + ./iverilog-initial_display + diff yosys-initial_display.log iverilog-initial_display.log + test_always_display clk -DEVENT_CLK + local subtest=clk + shift + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v Test: attrib06_operator_suffix -> ok Running from a child directory with content1.dat Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: test_simulation_seq -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:4$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:4$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 0de35d2746, CPU: user 0.03s system 0.01s, MEM: 28.30 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 39% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v Running from a child directory with temp/content2.dat Checking cnt1e.aig. xprop_or_1u1_1: ok xprop_or_1u1_1: ok KRunning from a child directory with content2.dat /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. [48]Dumping module `\m'. End of script. Logfile hash: e35e8bb689, CPU: user 0.03s system 0.01s, MEM: 27.83 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 39% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... Test: attrib08_mod_inst -> ok + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v + test_always_display clk_rst -DEVENT_CLK_RST + local subtest=clk_rst + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v Checking a failure when zero length filename is provided /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:7$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:7$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: c95608ddf0, CPU: user 0.03s system 0.01s, MEM: 28.54 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 41% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... memory.v:15: ERROR: Can not open file `` for \$readmemb. Execution failed, which is OK. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Checking a failure when not existing filename is provided + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v [49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb. Execution failed, which is OK. ...passed tests in tests/memfile /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: faf50513c3, CPU: user 0.03s system 0.01s, MEM: 28.24 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 39% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v + test_always_display star -DEVENT_STAR + local subtest=star + shift + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v [50]Checking empty.aig. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:10$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$always_display.v:10$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7b2c5274a5, CPU: user 0.03s system 0.01s, MEM: 28.69 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 40% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... Test: t_async_big -> ok + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v [14]Test: test_simulation_inc -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 8979c5de0b, CPU: user 0.03s system 0.01s, MEM: 28.60 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 38% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... [51]+ diff yosys-always_display-star-1.v yosys-always_display-star-2.v + test_always_display clk_en -DEVENT_CLK -DCOND_EN + local subtest=clk_en + shift + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:4$1'. 1/1: $display$0x7f83148c63a0:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. Removing empty process `m.$proc$always_display.v:4$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Warning: The new network has no primary inputs. It is recommended Optimizing module m. to add a dummy PI to make sure all commands work correctly. Warning: The current network has no primary outputs. Some commands may not work correctly. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Passed memory_bram test 01_04. Dumping module `\m'. End of script. Logfile hash: dd49b8291a, CPU: user 0.03s system 0.01s, MEM: 28.61 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 44% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... [13]+ ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v [52] Passed memory_bram test 02_00. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1/1: $write$0x7f6cdcb0f3a0:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. xprop_xor_1u1_1: ok xprop_xor_1u1_1: ok Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: d38c38dd5f, CPU: user 0.03s system 0.01s, MEM: 28.25 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 42% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN + local subtest=clk_rst_en + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v K Checking false.aig. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:7$1'. 1/1: $display$0x7f4d3d63e3a0:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. Removing empty process `m.$proc$always_display.v:7$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). [53]Optimizing module m. xprop_or_1s1_2: ok xprop_or_1s1_2: ok Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: d8cf87e5b9, CPU: user 0.03s system 0.01s, MEM: 28.33 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 44% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v Test: code_hdl_models_dff_async_reset -> ok cd tests/liberty && bash run-test.sh "" Testing on XNOR2X1.lib.. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1/1: $write$0x7f460b931030:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 15a035b746, CPU: user 0.03s system 0.01s, MEM: 27.84 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 41% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ... [54]+ diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v + test_always_display star_en -DEVENT_STAR -DCOND_EN + local subtest=star_en + shift + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. K /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: always_display.v Parsing Verilog input from `always_display.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$always_display.v:10$1'. 1/1: $display$0x7ff3ac2c53a0:15$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. Removing empty process `m.$proc$always_display.v:10$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 0054e7c947, CPU: user 0.03s system 0.01s, MEM: 28.57 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 43% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v xprop_or_2u2_2: ok xprop_or_2u2_2: ok Test: attrib09_case -> ok [15] Test: test_simulation_or -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1/1: $write$0x7f2debc903a0:20$2_EN 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Test: arrays01 -> ok Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 4. Executing Verilog backend. 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 0058917afd, CPU: user 0.03s system 0.01s, MEM: 28.17 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 43% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... [55]+ diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v Checking halfadder.aig. + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= + local subtest=dec_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: bfb187b86d, CPU: user 0.03s system 0.01s, MEM: 27.81 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v [56]xprop_xor_1s1_2: ok xprop_xor_1s1_2: ok make -C tests/arch/anlogic -f run-test.mk Test: code_hdl_models_dff_sync_reset -> ok Test: carryadd -> ok [14]make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/anlogic' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 4be9539e85, CPU: user 0.03s system 0.01s, MEM: 28.59 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 25% 1x clean (0 sec), 21% 2x read_verilog (0 sec), ... + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v Testing on busdef.lib.. + ./iverilog-roundtrip-dec_unsigned-1 + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v [57]+ ./iverilog-roundtrip-dec_unsigned-1 + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed + local subtest=dec_signed + shift + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v Test: attrib01_module -> ok make -C tests/arch/ecp5 -f run-test.mk Checking inverter.aig. Test: code_hdl_models_encoder_4to2_gates -> ok make -C tests/arch/efinix -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ecp5' make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/efinix' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: bbdfa5ca92, CPU: user 0.03s system 0.01s, MEM: 28.67 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 25% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v [58] Test: t_init_lut_zeros_any -> ok make -C tests/arch/gatemate -f run-test.mk /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gatemate' Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: b233de92a6, CPU: user 0.03s system 0.01s, MEM: 27.91 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 25% 1x clean (0 sec), 22% 2x read_verilog (0 sec), ... + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v Passed memory_bram test 02_01. + ./iverilog-roundtrip-dec_signed + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v [59]+ ./iverilog-roundtrip-dec_signed-1 Kmake -C tests/arch/gowin -f run-test.mk Test: test_simulation_decoder -> ok make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gowin' + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed-1 + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= + local subtest=hex_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v K /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v [15]Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 2377f2e106, CPU: user 0.03s system 0.01s, MEM: 28.56 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v [60]Checking notcnt1.aig. Test: attrib02_port_decl -> ok [16] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Testing on dff.lib.. Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 06bfea69c8, CPU: user 0.03s system 0.01s, MEM: 28.27 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 24% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v ...passed tests in tests/peepopt + ./iverilog-roundtrip-hex_unsigned [61]+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed + local subtest=hex_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v [62] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 824c3b1e65, CPU: user 0.03s system 0.01s, MEM: 28.57 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v + ./cxxrtl-test-value Checking notcnt1e.aig. + run_subtest value_fuzz + local subtest=value_fuzz + shift + g++ -std=c++11 -O2 -o cxxrtl-test-value_fuzz -I../../backends/cxxrtl/runtime test_value_fuzz.cc -lstdc++ Passed efinix-add_sub.ys Warning: define gw1n not used in the library. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: f18b3fa15b, CPU: user 0.03s system 0.01s, MEM: 28.62 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 25% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... [63]+ diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-hex_signed-1 Passed memory_bram test 03_00. + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= + local subtest=oct_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [64] xprop_xnor_1u1_1: ok xprop_xnor_1u1_1: ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: b768358a65, CPU: user 0.03s system 0.01s, MEM: 28.29 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v Testing on idranges.lib.. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v [65]Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 762621cd95, CPU: user 0.03s system 0.01s, MEM: 28.27 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 25% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... Checking or_.aig. + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v xprop_xor_2u2_2: ok xprop_xor_2u2_2: ok + ./iverilog-roundtrip-oct_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned-1 Passed memory_bram test 03_01. [66]+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v [17]+ ./iverilog-roundtrip-oct_unsigned-1 + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed + local subtest=oct_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v Test: attrib03_parameter -> ok Test: code_hdl_models_encoder_using_case -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Passed memory_bram test 02_04. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7ec82b15e3, CPU: user 0.03s system 0.01s, MEM: 28.57 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... [67]+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v Passed memory_bram test 01_03. Passed efinix-adffs.ys make -C tests/arch/ice40 -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ice40' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Checking symbols.aig. [68]Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: a747b9bd4f, CPU: user 0.03s system 0.01s, MEM: 29.01 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 28% 1x clean (0 sec), 19% 2x read_verilog (0 sec), ... + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v Testing on issue3498_bad.lib.. + ./iverilog-roundtrip-oct_signed Passed memory_bram test 03_02. + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed-1 Test: test_simulation_mux -> ok + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed-1 [69]+ diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= + local subtest=bin_unsigned + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v < | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 270b564880, CPU: user 0.03s system 0.01s, MEM: 28.24 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... Passed efinix-counter.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v Checking toggle-re.aig. Passed memory_bram test 02_03. Test: code_hdl_models_encoder_using_if -> ok [18][71] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. KRemoved 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: dc9f56cb10, CPU: user 0.03s system 0.01s, MEM: 27.48 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v xprop_xnor_1s1_2: ok + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v xprop_xnor_1s1_2: ok + ./iverilog-roundtrip-bin_unsigned + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned-1 Testing on non-ascii.lib.. [72]+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned-1 + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed + local subtest=bin_signed + shift + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v Warning: define gw1n not used in the library. Passed gowin-add_sub.ys [73] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1. Executing Verilog-2005 frontend: roundtrip.v Parsing Verilog input from `roundtrip.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$roundtrip.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7709253822, CPU: user 0.03s system 0.01s, MEM: 28.25 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 26% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v Checking toggle.aig. make -C tests/arch/intel_alm -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/intel_alm' Test: t_init_lut_val_zero -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. Cleaned up 1 empty switch. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. [74]Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\m'. End of script. Logfile hash: 7e2d8271c4, CPU: user 0.03s system 0.01s, MEM: 28.20 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 25% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v xprop_xnor_2u2_2: ok xprop_xnor_2u2_2: ok + ./iverilog-roundtrip-bin_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed-1 + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log Passed efinix-dffs.ys [75]+ diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log + test_cxxrtl always_full + local subtest=always_full + shift + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Test: asgn_binop -> ok Warning: define gw1n not used in the library. Test: t_sync_big_lut -> ok make -C tests/arch/machxo2 -f run-test.mk /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1. Executing Verilog-2005 frontend: always_full.v make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/machxo2' Parsing Verilog input from `always_full.v' to AST representation. Generating RTLIL representation for module `\always_full'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 207 redundant assignments. Promoted 207 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `always_full.$proc$always_full.v:3$1'. Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. Removed 0 unused cells and 207 unused wires. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. root of 0 design levels: always_full Automatically selected always_full as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \always_full 3.1.3. Analyzing design hierarchy.. Top module: \always_full Removed 0 unused modules. Module always_full directly or indirectly displays text -> setting "keep" attribute. 3.2. Executing FLATTEN pass (flatten design). 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). Testing on normal.lib.. 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. End of script. Logfile hash: af8795c7c4, CPU: user 0.05s system 0.02s, MEM: 29.36 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 37% 2x read_verilog (0 sec), 21% 2x write_cxxrtl (0 sec), ... Test: case_expr_const -> ok make -C tests/arch/microchip -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/microchip' + g++ -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++ Checking true.aig. [76]Kmake -C tests/arch/nanoxplore -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nanoxplore' Warning: define gw1n not used in the library. [77]Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. [78]Running io.ys. Warning: reg '\out' is assigned in a continuous assignment at < ok Running neg.ys. Passed anlogic-add_sub.ys Testing on processdefs.lib.. Test: t_init_lut_val_any -> ok Test: attrib04_net_var -> ok [80]Test: issue00335 -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memories' Testing expectations for amber23_sram_byte_en.v ..[81] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys -- Running command `test_cell -aigmap -w gate/ -n 1 -s 1 all' -- 1. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 2 new cells, skipped 0 cells. replaced 1 cell types: 1 $_ANDNOT_ 2. Executing AIGER backend. 3. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $_AND_ 4. Executing AIGER backend. 5. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 4 new cells, skipped 0 cells. replaced 1 cell types: 1 $_AOI3_ 6. Executing AIGER backend. 7. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 5 new cells, skipped 0 cells. replaced 1 cell types: 1 $_AOI4_ 8. Executing AIGER backend. 9. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 0 new cells, skipped 0 cells. replaced 1 cell types: 1 $_BUF_ 10. Executing AIGER backend. 11. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $_MUX_ 12. Executing AIGER backend. 13. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 2 new cells, skipped 0 cells. replaced 1 cell types: 1 $_NAND_ 14. Executing AIGER backend. 15. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 6 new cells, skipped 0 cells. replaced 1 cell types: 1 $_NMUX_ 16. Executing AIGER backend. 17. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 3 new cells, skipped 0 cells. replaced 1 cell types: 1 $_NOR_ 18. Executing AIGER backend. 19. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $_NOT_ 20. Executing AIGER backend. 21. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 6 new cells, skipped 0 cells. replaced 1 cell types: 1 $_OAI3_ 22. Executing AIGER backend. 23. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 10 new cells, skipped 0 cells. replaced 1 cell types: 1 $_OAI4_ 24. Executing AIGER backend. 25. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 3 new cells, skipped 0 cells. replaced 1 cell types: 1 $_ORNOT_ 26. Executing AIGER backend. 27. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 4 new cells, skipped 0 cells. replaced 1 cell types: 1 $_OR_ 28. Executing AIGER backend. 29. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 8 new cells, skipped 0 cells. replaced 1 cell types: 1 $_XNOR_ 30. Executing AIGER backend. 31. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $_XOR_ 32. Executing AIGER backend. 33. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 82 new cells, skipped 0 cells. replaced 1 cell types: 1 $add 34. Executing AIGER backend. 35. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 52 new cells, skipped 0 cells. replaced 1 cell types: 1 $alu 36. Executing AIGER backend. 37. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 6 new cells, skipped 0 cells. replaced 1 cell types: 1 $and 38. Executing AIGER backend. 39. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $bmux Warning: Skipping $bmux 40. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 0 new cells, skipped 0 cells. replaced 1 cell types: 1 $buf 41. Executing AIGER backend. 42. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $bwmux Warning: Skipping $bwmux 43. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $concat Warning: Skipping $concat 44. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $demux Warning: Skipping $demux 45. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $div Warning: Skipping $div 46. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $divfloor Warning: Skipping $divfloor 47. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 59 new cells, skipped 0 cells. replaced 1 cell types: 1 $eq 48. Executing AIGER backend. 49. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $fa Warning: Skipping $fa 50. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 3 new cells, skipped 0 cells. replaced 1 cell types: 1 $ge 51. Executing AIGER backend. 52. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 72 new cells, skipped 0 cells. replaced 1 cell types: 1 $gt 53. Executing AIGER backend. 54. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $lcu Warning: Skipping $lcu 55. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 77 new cells, skipped 0 cells. replaced 1 cell types: 1 $le 56. Executing AIGER backend. 57. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 23 new cells, skipped 0 cells. replaced 1 cell types: 1 $logic_and 58. Executing AIGER backend. 59. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $logic_not 60. Executing AIGER backend. 61. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 22 new cells, skipped 0 cells. replaced 1 cell types: 1 $logic_or 62. Executing AIGER backend. 63. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 55 new cells, skipped 0 cells. replaced 1 cell types: 1 $lt 64. Executing AIGER backend. 65. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $lut Warning: Skipping $lut 66. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $macc_v2 Warning: Skipping $macc_v2 67. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $mod Warning: Skipping $mod 68. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $modfloor Warning: Skipping $modfloor 69. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $mul Warning: Skipping $mul 70. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $mux 71. Executing AIGER backend. 72. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 45 new cells, skipped 0 cells. replaced 1 cell types: 1 $ne 73. Executing AIGER backend. 74. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $neg Warning: Skipping $neg 75. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 2 new cells, skipped 0 cells. replaced 1 cell types: 1 $not 76. Executing AIGER backend. 77. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $or 78. Executing AIGER backend. 79. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 0 new cells, skipped 0 cells. replaced 1 cell types: 1 $pos 80. Executing AIGER backend. 81. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 0 new cells, skipped 0 cells. replaced 1 cell types: 1 $reduce_and 82. Executing AIGER backend. 83. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 8 new cells, skipped 0 cells. replaced 1 cell types: 1 $reduce_bool 84. Executing AIGER backend. 85. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 4 new cells, skipped 0 cells. replaced 1 cell types: 1 $reduce_or 86. Executing AIGER backend. 87. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 40 new cells, skipped 0 cells. replaced 1 cell types: 1 $reduce_xnor 88. Executing AIGER backend. 89. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $reduce_xor 90. Executing AIGER backend. 91. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $shift Warning: Skipping $shift 92. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $shiftx Warning: Skipping $shiftx 93. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $shl Warning: Skipping $shl 94. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $shr Warning: Skipping $shr 95. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $slice Warning: Skipping $slice 96. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $sop Warning: Skipping $sop 97. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $sshl Warning: Skipping $sshl 98. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 0 cells with 0 new cells, skipped 1 cells. not replaced 1 cell types: 1 $sshr Warning: Skipping $sshr 99. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 8 new cells, skipped 0 cells. replaced 1 cell types: 1 $sub 100. Executing AIGER backend. 101. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 16 new cells, skipped 0 cells. replaced 1 cell types: 1 $xnor 102. Executing AIGER backend. 103. Executing AIGMAP pass (map logic to AIG). Module gold: replaced 1 cells with 7 new cells, skipped 0 cells. replaced 1 cell types: 1 $xor 104. Executing AIGER backend. Warnings: 22 unique messages, 22 total End of script. Logfile hash: e952e55d6c, CPU: user 0.04s system 0.02s, MEM: 26.67 MB peak Yosys Time spent: 40% 82x write_aiger (0 sec), 38% 63x aigmap (0 sec), ... ...passed tests in tests/aiger Passed memory_bram test 03_04. [82]Testing on retention.lib.. Warning: define gw1n not used in the library. [83]Passed intel_alm-add_sub.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed ecp5-add_sub.ys [84]Test: abc9 -> ok Passed gowin-compare.ys [85][86]Testing on semicolextra.lib.. Passed efinix-fsm.ys Passed gowin-counter.ys Passed ecp5-bug1459.ys ok. Testing expectations for implicit_en.v ..[87]Passed anlogic-counter.ys [16] ok. Testing expectations for issue00335.v ..Test: test_simulation_techmap -> ok [88][19]Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. Passed ecp5-bug1598.ys [20][89][90]Testing on semicolmissing.lib.. ok. Testing expectations for issue00710.v ..Test: case_expr_non_const -> ok [91]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! ok. Testing expectations for no_implicit_en.v ..[92]Passed machxo2-add_sub.ys Test: t_async_big_block -> ok [93] ok. Testing expectations for read_arst.v ..Passed intel_alm-blockram.ys [21][94]Testing on unquoted.lib.. ok. Testing expectations for read_two_mux.v ..Test: test_simulation_vlib -> ok Test: attrib06_operator_suffix -> ok ok. Testing expectations for shared_ports.v ..xprop_add_5u3_3: ok xprop_add_5u3_3: ok make -C tests/arch/nexus -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nexus' KRunning libcache.ys.. Passed memory_bram test 04_00. [95] ok. Testing expectations for simple_sram_byte_en.v ..Running options_test.ys.. K[96]KRunning read_liberty.ys.. K ok. Testing expectations for trans_addr_enable.v ..[97]Test: t_init_lut_val_no_undef -> ok Warning: Complex async reset for dff `\QN1'. Warning: Complex async reset for dff `\Q1'. ...passed tests in tests/liberty Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [98] ok. Testing expectations for trans_sdp.v ..Passed ecp5-bug1836.ys xprop_add_5s3_3: ok xprop_add_5s3_3: ok [99] ok. Testing expectations for trans_sp.v .. ...passed tests in tests/share ok. Testing expectations for wide_all.v ..Passed efinix-latches.ys ok. Testing expectations for wide_read_async.v ..Passed gowin-dffs.ys [17] ok. Testing expectations for wide_read_mixed.v ..Test: t_init_lut_val2_any -> ok Test: test_intermout -> ok [18]Passed machxo2-counter.ys ok. Testing expectations for wide_read_sync.v ..Test: code_hdl_models_full_adder_gates -> ok Test: t_init_lut_val2_no_undef -> ok [19]Test: attrib08_mod_inst -> ok [20] ok. Testing expectations for wide_read_trans.v ..Passed ecp5-bug2409.ys Passed intel_alm-adffs.ys Passed efinix-logic.ys ok. Testing expectations for wide_thru_priority.v ..Kmake -C tests/arch/quicklogic/pp3 -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/pp3' Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed gatemate-add_sub.ys ok. Testing expectations for wide_write.v ..KPassed anlogic-dffs.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed efinix-lutram.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. ok. ...passed tests in tests/memories Passed ice40-add_sub.ys Warning: Complex async reset for dff `\Q'. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: attrib09_case -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: t_init_lut_x_none -> ok Test: test_simulation_shifter -> ok Warning: Complex async reset for dff `\Q'. Warning: Complex async reset for dff `\Q'. Warning: Ignoring boxed module dffepc. Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop. Passed memory_bram test 04_01. Passed pp3-add_sub.ys Warning: Complex async reset for dff `\Q'. Warning: Ignoring boxed module dffepc. Passed intel_alm-counter.ys Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop. Passed pp3-counter.ys Test: const_branch_finish -> ok Test: t_init_lut_x_zero -> ok xprop_sub_5u3_3: ok xprop_sub_5u3_3: ok Passed gowin-adffs.ys Passed anlogic-fsm.ys [22]Passed memory_bram test 04_02. + ./cxxrtl-test-value_fuzz Randomized tests for value::shl: Passed machxo2-dffs.ys xprop_sub_5s3_3: ok xprop_sub_5s3_3: ok Passed pp3-fsm.ys Passed pp3-dffs.ys Warning: Ignoring boxed module dffepc. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop. Warning: define gw1n not used in the library. K[21]Test: carryadd -> ok Test: code_hdl_models_full_subtracter_gates -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_init_lut_x_no_undef -> ok xprop_mul_5u3_3: ok xprop_mul_5u3_3: ok Test: t_init_lut_x_any -> ok Passed efinix-shifter.ys Passed pp3-latches.ys [23]Warning: define gw1n not used in the library. xprop_mul_5s3_3: ok xprop_mul_5s3_3: ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed pp3-logic.ys Passed intel_alm-dffs.ys ERROR: FF myDFFP.$auto$ff.cc:337:slice$669 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination Expected error pattern 'unsupported initial value and async reset value combination' found !!! Passed gowin-init-error.ys Passed machxo2-fsm.ys Test: case_expr_const -> ok KTest: t_ram_18b2B -> ok Passed pp3-adffs.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed gatemate-counter.ys Passed efinix-tribuf.ys Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Passed ice40-bug1597.ys Passed efinix-mux.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/efinix' Test: const_fold_func -> ok ...passed tests in tests/arch/efinix Test: t_ram_9b1B -> ok [24]Passed ecp5-bug2731.ys KPassed gowin-fsm.ys Test: case_expr_non_const -> ok Test: code_hdl_models_cam -> ok KTest: test_simulation_xnor -> ok Test: t_ram_4b1B -> ok Passed intel_alm-logic.ys Passed machxo2-logic.ys Test: code_hdl_models_gray_counter -> ok Warning: define gw1n not used in the library. Passed intel_alm-fsm.ys Test: const_branch_finish -> ok Passed machxo2-adffs.ys Test: t_ram_2b1B -> ok Passed memory_bram test 04_03. make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bram' ...passed tests in tests/bram Passed ecp5-counter.ys [22]Kxprop_div_5u3_3: ok xprop_div_5u3_3: ok Passed anlogic-logic.ys Passed pp3-mux.ys Passed anlogic-blockram.ys [25]Test: t_ram_1b1B -> ok Passed ecp5-adffs.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: const_func_shadow -> ok Test: code_hdl_models_half_adder_gates -> ok Passed pp3-tribuf.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/pp3' ...passed tests in tests/arch/quicklogic/pp3 Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_init_9b1B_zeros_zero -> ok Test: t_init_9b1B_zeros_any -> ok Test: test_simulation_xor -> ok xprop_div_5s3_3: ok xprop_div_5s3_3: ok Test: const_fold_func -> ok Test: test_simulation_techmap_tech -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/hana' ...passed tests in tests/hana [23]Passed intel_alm-mul.ys Test: code_hdl_models_lfsr -> ok Test: t_init_9b1B_val_zero -> ok Test: constpower -> ok Test: t_init_9b1B_val_any -> ok xprop_mod_5u3_3: ok xprop_mod_5u3_3: ok Passed ice40-bug1598.ys Warning: define gw1n not used in the library. + ./yosys-always_full Passed anlogic-lutram.ys + iverilog -o iverilog-always_full always_full.v always_full_tb.v + ./iverilog-always_full + grep -v '\$finish called' + diff iverilog-always_full.log yosys-always_full.log + test_cxxrtl always_comb + local subtest=always_comb + shift + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1. Executing Verilog-2005 frontend: always_comb.v Parsing Verilog input from `always_comb.v' to AST representation. Generating RTLIL representation for module `\top'. Generating RTLIL representation for module `\sub'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$always_comb.v:3$13'. Set init value: \b = 1'0 Found init rule in `\top.$proc$always_comb.v:2$12'. Set init value: \a = 1'0 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1/1: $display$0x7f00516e5130:23$19_EN Creating decoders for process `\top.$proc$always_comb.v:3$13'. Creating decoders for process `\top.$proc$always_comb.v:2$12'. Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. created $dff cell `$procdff$22' with positive edge clock. Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. created $dff cell `$procdff$23' with positive edge clock. 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. Removing empty process `sub.$proc$always_comb.v:23$15'. Removing empty process `top.$proc$always_comb.v:3$13'. Removing empty process `top.$proc$always_comb.v:2$12'. Removing empty process `top.$proc$always_comb.v:8$1'. Cleaned up 1 empty switch. 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module sub. Optimizing module top. Removed 0 unused cells and 7 unused wires. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. root of 0 design levels: sub root of 1 design levels: top Automatically selected top as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \top Used module: \sub 3.1.3. Analyzing design hierarchy.. Top module: \top Used module: \sub Removed 0 unused modules. Module sub directly or indirectly displays text -> setting "keep" attribute. Module top directly or indirectly displays text -> setting "keep" attribute. 3.2. Executing FLATTEN pass (flatten design). Deleting now unused module sub. 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. End of script. Logfile hash: 3870b0b352, CPU: user 0.04s system 0.01s, MEM: 28.98 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 31% 2x opt_expr (0 sec), 17% 1x clean (0 sec), ... K+ g++ -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++ Test: code_hdl_models_lfsr_updown -> ok Test: t_init_9b1B_val_no_undef -> ok Passed gatemate-fsm.ys Passed gowin-logic.ys Test: constmuldivmod -> ok [24]Test: t_init_13b2B_val_any -> ok Test: const_func_shadow -> ok [25]Test: code_hdl_models_mux_2to1_gates -> ok [26]Warning: define gw1n not used in the library. [27]Passed anlogic-latches.ys Test: t_init_18b2B_val_any -> ok make -C tests/arch/quicklogic/qlf_k6n10f -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/qlf_k6n10f' Test: dff_different_styles -> ok Test: t_init_18b2B_val_no_undef -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. xprop_mod_5s3_3: ok xprop_mod_5s3_3: ok Passed ecp5-dffs.ys Passed anlogic-shifter.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. [28]Test: t_init_4b1B_x_none -> ok [29][30]Test: code_hdl_models_mux_using_assign -> ok [31]Passed intel_alm-shifter.ys [32][33][34]Test: t_init_4b1B_x_zero -> ok [35][36][37][38][39][40]Test: t_init_4b1B_x_any -> ok + ./yosys-always_comb Passed intel_alm-mux.ys [26]+ iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v Test: code_hdl_models_mux_using_case -> ok + grep -v '\$finish called' + [41]./iverilog-always_comb + diff iverilog-always_comb.log yosys-always_comb.log + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v [42] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog always_full.v; prep; clean' -- 1. Executing Verilog-2005 frontend: always_full.v Parsing Verilog input from `always_full.v' to AST representation. Generating RTLIL representation for module `\always_full'. Successfully finished Verilog frontend. 2. Executing PREP pass. 2.1. Executing HIERARCHY pass (managing design hierarchy). Module always_full directly or indirectly displays text -> setting "keep" attribute. 2.2. Executing PROC pass (convert processes to netlists). 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 207 redundant assignments. Promoted 207 assignments to connections. 2.2.4. Executing PROC_INIT pass (extract init attributes). 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `always_full.$proc$always_full.v:3$1'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.3. Executing FUTURE pass. 2.4. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. Removed 0 unused cells and 207 unused wires. 2.6. Executing CHECK pass (checking for obvious problems). Checking module always_full... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Computing hashes of 207 cells of `\always_full'. Finding duplicate cells in `\always_full'. Removed a total of 0 cells. 2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \always_full.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \always_full. Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Computing hashes of 207 cells of `\always_full'. Finding duplicate cells in `\always_full'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.7.7. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.7.8. Finished fast OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. 2.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\always_full'. Computing hashes of 207 cells of `\always_full'. Finding duplicate cells in `\always_full'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \always_full.. 2.11.4. Finished fast OPT passes. 2.12. Printing statistics. === always_full === +----------Local Count, excluding submodules. | 1 wires 1 wire bits 1 public wires 1 public wire bits 1 ports 1 port bits 207 cells 207 $print 2.13. Executing CHECK pass (checking for obvious problems). Checking module always_full... Found and reported 0 problems. -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 3. Executing Verilog backend. 3.1. Executing BMUXMAP pass. 3.2. Executing DEMUXMAP pass. Dumping module `\always_full'. End of script. Logfile hash: f75bd4543e, CPU: user 0.07s system 0.02s, MEM: 30.08 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 22% 4x opt_clean (0 sec), 20% 2x read_verilog (0 sec), ... [43]Passed gatemate-dffs.ys + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v + ./iverilog-always_full-1 + grep -v '\$finish called' + diff iverilog-always_full.log iverilog-always_full-1.log + ../../yosys -p 'read_verilog display_lm.v' [44]+ ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1. Executing Verilog-2005 frontend: display_lm.v Parsing Verilog input from `display_lm.v' to AST representation. Generating RTLIL representation for module `\top'. Generating RTLIL representation for module `\mid'. Generating RTLIL representation for module `\bot'. %l: \bot %m: \bot Successfully finished Verilog frontend. 2. Executing CXXRTL backend. 2.1. Executing HIERARCHY pass (managing design hierarchy). 2.1.1. Finding top of design hierarchy.. root of 0 design levels: bot root of 1 design levels: mid root of 2 design levels: top Automatically selected top as design top module. 2.1.2. Analyzing design hierarchy.. Top module: \top Used module: \mid Used module: \bot 2.1.3. Analyzing design hierarchy.. Top module: \top Used module: \mid Used module: \bot Removed 0 unused modules. Module bot directly or indirectly displays text -> setting "keep" attribute. Module mid directly or indirectly displays text -> setting "keep" attribute. Module top directly or indirectly displays text -> setting "keep" attribute. 2.2. Executing FLATTEN pass (flatten design). Deleting now unused module bot. Deleting now unused module mid. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 2 assignments to connections. 2.3.4. Executing PROC_INIT pass (extract init attributes). 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:10$3'. Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:10$3'. Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. Cleaned up 0 empty switches. 2.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. End of script. Logfile hash: ba0468a5ee, CPU: user 0.03s system 0.01s, MEM: 28.61 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 36% 1x opt_expr (0 sec), 21% 2x read_verilog (0 sec), ... + g++ -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ [45]Test: t_init_4b1B_x_no_undef -> ok [46]xprop_divfloor_5u3_3: ok xprop_divfloor_5u3_3: ok KPassed intel_alm-lutram.ys [47]Passed anlogic-mux.ys Passed ecp5-dpram.ys [48]Test: code_hdl_models_mux_using_if -> ok Test: t_clock_a4_wANYrANYsFalse -> ok Passed machxo2-mux.ys Passed intel_alm-tribuf.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/intel_alm' ...passed tests in tests/arch/intel_alm Passed gowin-init.ys Test: t_clock_a4_wANYrNEGsFalse -> ok Warning: define gw1n not used in the library. Passed gatemate-logic.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_hdl_models_one_hot_cnt -> ok Test: t_clock_a4_wANYrPOSsFalse -> ok Passed ice40-bug1626.ys Passed anlogic-tribuf.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/anlogic' ...passed tests in tests/arch/anlogic + ./yosys-display_lm_cc + for log in yosys-display_lm.log yosys-display_lm_cc.log + grep '^%l: \\bot$' yosys-display_lm.log %l: \bot + grep '^%m: \\bot$' yosys-display_lm.log %m: \bot + for log in yosys-display_lm.log yosys-display_lm_cc.log + grep '^%l: \\bot$' yosys-display_lm_cc.log %l: \bot %l: \bot + grep '^%m: \\bot$' yosys-display_lm_cc.log %m: \bot %m: \bot ...passed tests in tests/fmt Test: t_clock_a4_wNEGrANYsFalse -> ok xprop_divfloor_5s3_3: ok xprop_divfloor_5s3_3: ok [49]Passed qlf_k6n10f-add_sub.ys Passed ecp5-fsm.ys Test: code_hdl_models_parallel_crc -> ok Test: constpower -> ok Test: t_clock_a4_wNEGrPOSsFalse -> ok Warning: Wire adff.q has an unprocessed 'init' attribute. Warning: Complex async reset for dff `\Q'. [50][51]Passed machxo2-shifter.ys Test: t_clock_a4_wNEGrNEGsFalse -> ok [52]Passed nexus-counter.ys [53]Test: code_hdl_models_parity_using_assign -> ok [54][55]Test: code_hdl_models_parity_using_bitwise -> ok [56]Passed ice40-adffs.ys [57][58][59]Test: t_clock_a4_wPOSrANYsFalse -> ok [60]xprop_modfloor_5u3_3: ok xprop_modfloor_5u3_3: ok [61][62][63]Passed microchip-dff_opt.ys [64]Test: constmuldivmod -> ok [65][66]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. [67]Test: code_hdl_models_parity_using_function -> ok Test: dff_init -> ok Test: t_clock_a4_wPOSrNEGsFalse -> ok [68]Passed gatemate-adffs.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed gowin-mux.ys Test: t_clock_a4_wPOSrPOSsFalse -> ok Passed machxo2-lutram.ys [27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed ecp5-latches_abc9.ys Passed machxo2-tribuf.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/machxo2' ...passed tests in tests/arch/machxo2 Test: t_clock_a4_wANYrANYsTrue -> ok KWarning: Complex async reset for dff `\Q'. [69]Passed qlf_k6n10f-counter.ys [70][71]KTest: code_hdl_models_pri_encoder_using_assign -> ok [72]xprop_modfloor_5s3_3: ok xprop_modfloor_5s3_3: ok [73]Test: t_clock_a4_wNEGrPOSsTrue -> ok Test: code_hdl_models_rom_using_case -> ok Test: t_clock_a4_wNEGrNEGsTrue -> ok Test: t_clock_a4_wPOSrNEGsTrue -> ok Passed ecp5-logic.ys Warning: Wire adffn.q has an unprocessed 'init' attribute. Passed ecp5-latches.ys xprop_lt_5u3_2: ok xprop_lt_5u3_2: ok Passed gatemate-latches.ys Test: code_hdl_models_serial_crc -> ok Test: t_clock_a4_wPOSrPOSsTrue -> ok Test: t_unmixed -> ok Test: code_hdl_models_tff_async_reset -> ok Passed ice40-bug2061.ys Test: dff_different_styles -> ok Test: t_mixed_9_18 -> ok xprop_lt_5s3_2: ok xprop_lt_5s3_2: ok Passed nexus-fsm.ys Test: code_hdl_models_tff_sync_reset -> ok Test: dff_init -> ok Test: t_mixed_18_9 -> ok Test: t_mixed_36_9 -> ok Test: fiedler-cooley -> ok [74][75]Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::shr: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sshr: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::add: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sub: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::ctlz: Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::udivmod (div): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42[76][77]Test: t_mixed_4_2 -> ok Test: case_large -> ok xprop_le_5s3_2: ok xprop_le_5s3_2: ok [78]xprop_le_5u3_2: ok xprop_le_5u3_2: ok Test: t_tdp -> ok Passed nexus-logic.ys [79]Test: code_hdl_models_uart -> ok Test: t_sync_2clk -> ok Passed microchip-reduce.ys Warning: Wire dffs.q has an unprocessed 'init' attribute. Passed ecp5-macc.ys Test: t_sync_shared -> ok [28]xprop_eq_5u3_2: ok xprop_eq_5u3_2: ok Test: forgen01 -> ok Test: code_hdl_models_up_counter -> ok Test: t_sync_2clk_shared -> ok Warning: Wire my_dffe.q has an unprocessed 'init' attribute. Passed qlf_k6n10f-dffs.ys Test: t_sync_trans_old_old -> ok Test: case_large -> ok Test: code_hdl_models_up_counter_load -> ok Test: t_sync_trans_old_new -> ok Passed nexus-add_sub.ys xprop_eq_5s3_2: ok xprop_eq_5s3_2: ok Test: dynslice -> ok xprop_ne_5u3_2: ok xprop_ne_5u3_2: ok Test: t_sync_trans_old_none -> ok Passed ecp5-lutram.ys TWarning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: t_sync_trans_new_old -> ok xprop_ne_5s3_2: ok xprop_ne_5s3_2: ok [80]xprop_eqx_5u3_2: ok xprop_eqx_5u3_2: ok Warning: define gw1n not used in the library. Test: t_sync_trans_new_new -> ok Test: code_hdl_models_up_down_counter -> ok Passed nexus-blockram.ys Test: fiedler-cooley -> ok Test: forgen02 -> ok xprop_eqx_5s3_2: ok xprop_eqx_5s3_2: ok Test: t_sync_trans_new_none -> ok Passed gowin-shifter.ys make -C tests/arch/xilinx -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/arch/xilinx' Passed ecp5-mul.ys Test: t_sp_nc_none -> ok Test: forgen01 -> ok Passed qlf_k6n10f-div.ys Passed gatemate-mul.ys Warning: Wire ndffnr.q has an unprocessed 'init' attribute. Passed qlf_k6n10f-adffs.ys Test: t_sp_new_none -> ok Test: code_specman_switch_fabric -> ok Passed nexus-dffs.ys xprop_nex_5u3_2: ok xprop_nex_5u3_2: ok Test: t_sp_old_none -> ok Passed microchip-uram_ar.ys Test: forgen02 -> ok Passed gatemate-luttrees.ys Passed nanoxplore-fsm.ys Test: fsm -> ok Test: code_tidbits_asyn_reset -> ok Test: t_sp_nc_nc -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: forloops -> ok Test: func_recurse -> ok Test: code_tidbits_blocking -> ok Test: forloops -> ok Test: func_block -> ok Test: t_sp_new_nc -> ok xprop_nex_5s3_2: ok xprop_nex_5s3_2: ok [81]Test: t_sp_old_nc -> ok xprop_ge_5u3_2: ok xprop_ge_5u3_2: ok Test: code_tidbits_fsm_using_always -> ok xprop_ge_5s3_2: ok xprop_ge_5s3_2: ok Passed nexus-lutram.ys Passed ice40-counter.ys make -C tests/bugpoint -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/bugpoint' ERROR: Missing -script or -command option. Expected error pattern 'Missing -script or -command option.' found !!! xprop_gt_5u3_2: ok xprop_gt_5u3_2: ok ERROR: The provided script file or command and Yosys binary do not crash on this design! Expected error pattern 'do not crash on this design' found !!! Test: t_sp_nc_new -> ok Passed nanoxplore-logic.ys xprop_reduce_and_3u_3: ok Passed nexus-shifter.ys xprop_reduce_and_3u_3: ok [29]Passed gatemate-shifter.ys ERROR: The provided script file or command and Yosys binary returned value 3 instead of expected 7 on this design! Expected error pattern 'returned value 3 instead of expected 7' found !!! ERROR: The provided grep string is not found in the log file! Expected error pattern 'not found in the log file!' found !!! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! xprop_gt_5s3_2: ok xprop_gt_5s3_2: ok Warning: define gw1n not used in the library. xprop_reduce_and_3s_3: ok xprop_reduce_and_3s_3: ok ERROR: The provided grep string is not found in stderr log! Expected error pattern 'not found in stderr log!' found !!! Passed bugpoint-failures.ys Test: func_width_scope -> ok Passed microchip-simple_ram.ys Test: t_sp_new_new -> ok KTest: code_tidbits_fsm_using_function -> ok Test: fsm -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: genblk_collide -> ok Passed gatemate-mux.ys Passed gowin-tribuf.ys Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15. Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16. Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21. Test: t_sp_old_new -> ok Passed ecp5-opt_lut_ins.ys [82]Test: code_tidbits_fsm_using_single_always -> ok Test: t_sp_nc_old -> ok Test: func_block -> ok Test: genblk_dive -> ok ERROR: No 'raise_error' attribute found xprop_reduce_or_3u_3: ok xprop_reduce_or_3u_3: ok ERROR: No 'raise_error' attribute found Test: t_sp_new_old -> ok ERROR: No 'raise_error' attribute found ERROR: No 'raise_error' attribute found ERROR: No 'raise_error' attribute found Test: genblk_order -> ok ERROR: help me xprop_reduce_or_3s_3: ok xprop_reduce_or_3s_3: ok ERROR: help me Test: code_tidbits_nonblocking -> ok ERROR: help me Test: t_sp_old_old -> ok Test: genblk_port_shadow -> ok ERROR: No 'raise_error' attribute found Passed bugpoint-raise_error.ys make -C tests/opt -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/opt' Test: t_sp_nc_new_only -> ok Passed opt-alumacc.ys Test: code_tidbits_reg_combo_example -> ok Passed opt-bug1525.ys Passed opt-bug1758.ys Passed ecp5-rom.ys [30]Passed opt-bug1854.ys Passed opt-bug2010.ys Passed opt-bug2221.ys Passed opt-bug2311.ys Passed opt-bug2318.ys Passed opt-bug2623.ys Passed opt-bug2765.ys Passed qlf_k6n10f-fsm.ys xprop_reduce_xor_3u_3: ok xprop_reduce_xor_3u_3: ok Passed opt-bug2824.ys Test: dynslice -> ok Test: t_sp_new_new_only -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed gatemate-memory.ys Passed opt-bug2766.ys Passed opt-bug2920.ys Test: code_tidbits_reg_seq_example -> ok Passed opt-bug3047.ys Passed opt-bug3117.ys Passed opt-bug3848.ys Test: t_sp_old_new_only -> ok Passed opt-bug3867.ys Passed bugpoint-proc_constraints.ys Test: func_recurse -> ok Passed opt-bug4413.ys Passed opt-bug4610.ys Passed opt-bug5164.ys Passed opt-bug5398.ys Passed opt-memory_bmux2rom.ys Passed gatemate-tribuf.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gatemate' ...passed tests in tests/arch/gatemate Test: t_sp_nc_new_only_be -> ok Test: code_tidbits_syn_reset -> ok Passed opt-memory_dff_trans.ys Test: code_tidbits_wire_example -> ok [31]Test: func_width_scope -> ok xprop_reduce_xnor_3u_3: ok xprop_reduce_xnor_3u_3: ok Kxprop_reduce_xor_3s_3: ok xprop_reduce_xor_3s_3: ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: t_sp_new_new_only_be -> ok Passed opt-memory_map_offset.ys Test: code_verilog_tutorial_addbit -> ok Warning: Feature 'open_balance_tree' is experimental. Test: genblk_collide -> ok Passed ecp5-shifter.ys Test: t_sp_old_new_only_be -> ok Test: genblk_dive -> ok Test: code_verilog_tutorial_always_example -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_nc_new_be -> ok Passed opt-opt_balance_tree.ys Test: graphtest -> ok Passed opt-opt_clean_mem.ys [83]Test: genblk_order -> ok Passed opt-opt_clean_init.ys make -C tests/sat -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sat' Passed opt-opt_clean_standalone_wires.ys xprop_reduce_xnor_3s_3: ok xprop_reduce_xnor_3s_3: ok Passed sat-asserts.ys Passed opt-opt_dff-simplify.ys ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top/c_c top/c_b top/c_a top/w_c top/w_b top/w_a Test: code_verilog_tutorial_bus_con -> ok Test: t_sp_new_new_be -> ok Passed sat-asserts_seq.ys ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top/c_a top/c_b top/w_a top/w_b top/w_c Passed sat-bug2595.ys Warning: Complex async reset for dff `\q [12]'. Warning: Complex async reset for dff `\q [8]'. Passed ecp5-tribuf.ys Passed opt-opt_dff_arst.ys Test: genblk_port_shadow -> ok ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top/c_b top/c_a top/w_c top/w_b top/w_a ERROR: Assertion failed: selection is not empty: w:w_a %co* w:w_c %ci* %i Selection contains: top top/c_b top/c_a top/w_a top/w_b top/w_c Passed opt-opt_dff_clk.ys Passed nexus-tribuf.ys Test: code_verilog_tutorial_comment -> ok Test: t_sp_old_new_be -> ok . Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::udivmod (mod): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sdivmod (div): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. Randomized tests for value::sdivmod (mod): Test passed @ Bits = 8. Test passed @ Bits = 32. Test passed @ Bits = 42. Test passed @ Bits = 63. Test passed @ Bits = 64. + ../../yosys -p 'read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc' Passed sat-counters-repeat.ys [84] /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) -- Running command `read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc' -- 1. Executing Verilog-2005 frontend: test_unconnected_output.v Parsing Verilog input from `test_unconnected_output.v' to AST representation. Generating RTLIL representation for module `\blackbox'. Generating RTLIL representation for module `\unconnected_output'. test_unconnected_output.v:19: Warning: Identifier `\clock' is implicitly declared. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4. Executing PROC_INIT pass (extract init attributes). 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). Warning: Ignoring boxed module blackbox. Optimizing module unconnected_output. 3. Executing CXXRTL backend. 3.1. Executing HIERARCHY pass (managing design hierarchy). 3.1.1. Finding top of design hierarchy.. Warning: Ignoring boxed module blackbox. root of 1 design levels: unconnected_output Automatically selected unconnected_output as design top module. 3.1.2. Analyzing design hierarchy.. Top module: \unconnected_output 3.1.3. Analyzing design hierarchy.. Top module: \unconnected_output Removed 0 unused modules. Warning: Resizing cell port unconnected_output.bb.out1 from 1 bits to 8 bits. 3.2. Executing FLATTEN pass (flatten design). 3.3. Executing PROC pass (convert processes to netlists). 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.3.4. Executing PROC_INIT pass (extract init attributes). 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.3.12. Executing OPT_EXPR pass (perform const folding). Warning: Ignoring boxed module blackbox. Optimizing module unconnected_output. Warnings: 3 unique messages, 5 total End of script. Logfile hash: 5ce3cff38f, CPU: user 0.03s system 0.01s, MEM: 27.86 MB peak Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3) Time spent: 32% 2x opt_expr (0 sec), 17% 1x clean (0 sec), ... + g++ -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc Passed opt-opt_dff_const.ys < ok < ok Test: graphtest -> ok xprop_reduce_bool_1u_1: ok xprop_reduce_bool_1u_1: ok Test: t_sp_new_old_be -> ok Test: t_sp_old_old_be -> ok Passed ice40-dffs.ys Test: t_sp_nc_nc_be -> ok Passed opt-opt_dff_en.ys Test: code_verilog_tutorial_d_ff -> ok Passed microchip-uram_sr.ys Test: t_sp_new_nc_be -> ok Passed nanoxplore-shifter.ys Passed opt-opt_dff_qd.ys Passed opt-opt_dff_mux.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. xprop_reduce_bool_3u_3: ok xprop_reduce_bool_3u_3: ok make -C tests/sdc -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sdc' Test: t_sp_old_nc_be -> ok Warning: Feature 'sdc' is experimental. Passed sdc-alu_sub.ys Passed bugpoint-mod_constraints.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/bugpoint' ...passed tests in tests/bugpoint Passed sdc-side-effects.sh Test: code_verilog_tutorial_decoder -> ok Passed sdc-unknown-getter.sh make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sdc' ...passed tests in tests/sdc xprop_reduce_bool_3s_3: ok xprop_reduce_bool_3s_3: ok xprop_reduce_bool_3s_1: ok Passed sat-counters.ys xprop_reduce_bool_3s_1: ok Passed sat-dff.ys ...passed tests in tests/cxxrtl xprop_logic_not_1u_1: ok xprop_logic_not_1u_1: ok Test: t_sp_nc_auto -> ok Passed opt-opt_dff_srst.ys xprop_logic_not_3u_3: ok xprop_logic_not_3u_3: ok [85]Test: t_sp_new_auto -> ok Test: code_verilog_tutorial_decoder_always -> ok [32]Test: hierarchy -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_verilog_tutorial_escape_id -> ok Test: t_sp_old_auto -> ok xprop_logic_not_3s_3: ok xprop_logic_not_3s_3: ok Passed opt-opt_dff_sr.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed gowin-lutram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/gowin' ...passed tests in tests/arch/gowin KWarning: Shift register inference not yet supported for family xc3s. Passed opt-opt_expr.ys Passed sat-expose_dff.ys Passed nanoxplore-tribuf.ys Test: t_sp_nc_auto_be -> ok [86]Passed opt-opt_expr_alu.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed opt-opt_expr_and.ys Passed opt-opt_expr_cmp.ys Warning: wire '\a' is assigned in a block at < ok Passed opt-opt_expr_constconn.ys Test: t_sp_new_auto_be -> ok Passed opt-opt_expr_consumex.ys Test: code_verilog_tutorial_explicit -> ok Warning: Resizing cell port pre_post_adder.$mul$< ok xprop_logic_not_3s_1: ok xprop_logic_not_3s_1: ok [33]Passed opt-opt_expr_mux_undef.ys Test: code_verilog_tutorial_first_counter -> ok Passed opt-opt_expr_or.ys < ok Passed opt-opt_expr_xnor.ys Passed opt-opt_expr_xor.ys Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. Test: code_verilog_tutorial_flip_flop -> ok Passed microchip-ram_SDP.ys Test: hierdefparam -> ok [34]Test: t_sp_init_x_x_re -> ok Passed sat-grom.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed sat-initval.ys xprop_logic_and_1u1_1: ok xprop_logic_and_1u1_1: ok Passed qlf_k6n10f-logic.ys Passed ice40-fsm.ys Test: code_verilog_tutorial_fsm_full -> ok Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. KTest: ifdef_1 -> ok Test: i2c_master_tests -> ok Passed microchip-mult.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: ifdef_2 -> ok Test: t_sp_init_x_x_ce -> ok Test: t_sp_init_0_x -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: ifdef_1 -> ok Test: code_verilog_tutorial_good_code -> ok Test: t_sp_init_0_x_re -> ok Passed opt-opt_lut_elim.ys make -C tests/sim -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/sim' Test: t_sp_init_0_0 -> ok KPassed sim-assume_x_first_step.ys Passed sim-sim_adff.ys Passed sim-sim_adffe.ys Passed sim-sim_adlatch.ys T[35]Warning: Async reset value `\ad' is not constant! Passed sim-sim_aldff.ys Test: localparam_attr -> ok Warning: Async reset value `\ad' is not constant! Passed sim-sim_aldffe.ys Warning: Wire top.\cnt [7] is used but has no driver. Warning: Wire top.\cnt [6] is used but has no driver. Warning: Wire top.\cnt [5] is used but has no driver. Warning: Wire top.\cnt [4] is used but has no driver. Warning: Wire top.\cnt [3] is used but has no driver. Warning: Wire top.\cnt [2] is used but has no driver. Warning: Wire top.\cnt [1] is used but has no driver. Warning: Wire top.\cnt [0] is used but has no driver. Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000' ERROR: Signal difference Expected error pattern 'Signal difference' found !!! Passed sat-sim_counter.ys Passed sim-sim_cycles.ys Test: code_verilog_tutorial_if_else -> ok Passed sim-sim_dff.ys Test: t_sp_init_0_0_re -> ok xprop_logic_and_3u3_3: ok xprop_logic_and_3u3_3: ok Passed sim-sim_dffe.ys Warning: Complex async reset for dff `\q'. Test: ifdef_2 -> ok [36]Passed sim-sim_dffsr.ys Test: i2c_master_tests -> ok Passed sim-sim_dlatch.ys Passed sim-sim_dlatchsr.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed sim-sim_sdff.ys Passed microchip-ram_TDP.ys Passed sim-sim_sdffce.ys Test: hierdefparam -> ok Passed sim-sim_sdffe.ys Test: t_sp_init_0_any -> ok Test: localparam_attr -> ok Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_verilog_tutorial_multiply -> ok Passed sim-vcd_var_reference_whitespace.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sim' ...passed tests in tests/sim KPassed opt-opt_lut_ins.ys [87]Test: loop_prefix_case -> ok Passed opt-opt_lut_port.ys Passed ice40-ice40_dsp.ys Passed sat-sizebits.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed opt-opt_mem_priority.ys Passed sat-share.ys Passed sat-splice.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/sat' ...passed tests in tests/sat Test: t_sp_init_0_any_re -> ok [88]Test: code_verilog_tutorial_mux_21 -> ok [89]K[37]Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. [90]Passed xilinx-bug3670.ys [91]/home/buildozer/aports/testing/yosys/src/share/ice40/cells_sim.v:41: Warning: Yosys has only limited support for tri-state logic at the moment. Test: t_sp_init_v_x -> ok xprop_logic_and_3s3_3: ok xprop_logic_and_3s3_3: ok [92]Test: loop_prefix_case -> ok [93]Passed xilinx-add_sub.ys [94]Test: code_verilog_tutorial_n_out_primitive -> ok [95][96]Test: t_sp_init_v_x_re -> ok [97]Test: t_sp_init_v_0 -> ok Passed opt-opt_lut.ys Warning: Wire top.\t is used but has no driver. Warning: Wire top.\in is used but has no driver. Passed opt-opt_merge_init.ys make -C tests/svtypes -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/svtypes' [98]Passed opt-opt_merge_basic.ys Test: t_sp_init_v_0_re -> ok Passed opt-opt_merge_keep.ys Passed svtypes-enum_simple.ys Passed opt-opt_merge_properties.ys [99]Passed nexus-adffs.ys Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed svtypes-logic_rom.ys < ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/opt_share' ...passed tests in tests/opt_share < ok < ok Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1937_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1946_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1934_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1940_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1925_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1949_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1928_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1943_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1931_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1955_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1952_gate ($adff). Consider running `async2sync` or `clk2fflogic` first. Warning: No SAT model available for async FF cell $techmap$mul$< ok Passed svtypes-struct_dynamic_range.ys Test: loop_var_shadow -> ok Passed ice40-ice40_dsp_const.ys Test: code_verilog_tutorial_parity -> ok Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19. Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19. Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19. Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19. Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19. Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19. Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19. Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19. Passed svtypes-typedef_initial_and_assign.ys Passed svtypes-typedef_memory.ys K[38]Passed svtypes-typedef_memory_2.ys xprop_logic_and_3s3_1: ok xprop_logic_and_3s3_1: ok Passed svtypes-typedef_struct_global.ys Test: loop_var_shadow -> ok Passed qlf_k6n10f-latches.ys Passed opt-opt_pow.ys make -C tests/techmap -f run-test.mk Passed opt-opt_reduce_andor.ys make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/techmap' Passed svtypes-typedef_struct_port.ys Passed svtypes-multirange_array.sv Test: t_sp_arst_x_x -> ok [39]Passed svtypes-static_cast_simple.sv Test: code_verilog_tutorial_simple_function -> ok struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef. struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef. struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef. struct_array.sv:45: Warning: Range [3:-4] select out of bounds on signal `\s_s': Setting 4 LSB bits to undef. struct_array.sv:46: Warning: Range select [23:16] out of bounds on signal `\s_s': Setting all 8 result bits to undef. struct_array.sv:47: Warning: Range [19:12] select out of bounds on signal `\s_s': Setting 4 MSB bits to undef. struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef. struct_array.sv:38: Warning: Range [-1:-8] select out of bounds on signal `\s_s': Setting 8 LSB bits to undef. Test: generate -> ok Passed svtypes-struct_array.sv Passed svtypes-struct_simple.sv Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed opt-opt_mem_feedback.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed svtypes-struct_sizebits.sv xprop_logic_or_1u1_1: ok xprop_logic_or_1u1_1: ok Passed opt-opt_reduce_bmux.ys Passed svtypes-typedef_package.sv Test: t_sp_arst_x_x_re -> ok Passed svtypes-typedef_param.sv Passed opt-opt_reduce_demux.ys Passed svtypes-typedef_scopes.sv Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver. Test: code_verilog_tutorial_simple_if -> ok Passed svtypes-typedef_simple.sv Passed svtypes-typedef_struct.sv Passed svtypes-union_simple.sv make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/svtypes' ...passed tests in tests/svtypes Passed opt-opt_rmdff_sat.ys Test: macro_arg_surrounding_spaces -> ok Test: t_sp_arst_0_x -> ok Test: loops -> ok Test: code_verilog_tutorial_task_global -> ok Passed techmap-abc_state.ys [40]xprop_logic_or_3u3_3: ok xprop_logic_or_3u3_3: ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: macro_arg_surrounding_spaces -> ok Passed opt-opt_rmdff.ys Test: t_sp_arst_0_x_re -> ok Passed xilinx-bug1460.ys Passed xilinx-bug1462.ys Test: loops -> ok KPassed opt-opt_share_add_sub.ys Passed opt-opt_share_bug2334.ys Passed ice40-ice40_wrapcarry.ys Passed opt-opt_share_bug2335.ys Warning: wire '\Q' is assigned in a block at < ok Test: t_sp_arst_0_0 -> ok Test: t_sp_arst_0_any -> ok Test: t_sp_arst_0_0_re -> ok [41]Passed opt-opt_share_cat.ys Passed opt-opt_share_cat_multiuser.ys Test: macros -> ok Test: code_verilog_tutorial_v2k_reg -> ok Passed opt-opt_share_diff_port_widths.ys Passed nanoxplore-dffs.ys make -C tests/various -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/various' Test: t_sp_arst_0_any_re -> ok Passed opt-opt_share_extend.ys Warning: Wire abc9_test027.$abc$89$o is used but has no driver. xprop_logic_or_3s3_3: ok xprop_logic_or_3s3_3: ok Passed techmap-abc9.ys [42]Passed opt-opt_share_large_pmux_cat.ys Test: macros -> ok Passed ice40-dpram.ys Passed techmap-aigmap.ys Test: t_sp_arst_0_init -> ok Warning: Resizing cell port top.s0.f.j from 2 bits to 1 bits. Passed techmap-autopurge.ys Passed opt-opt_share_large_pmux_cat_multipart.ys Passed techmap-bmuxmap_pmux.ys Passed opt-opt_share_large_pmux_multipart.ys Test: code_verilog_tutorial_which_clock -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/asicworld' ...passed tests in tests/asicworld xprop_logic_or_3s3_1: ok xprop_logic_or_3s3_1: ok Passed xilinx-bug1480.ys Passed opt-opt_share_large_pmux_part.ys Passed opt-opt_share_mux_tree.ys Test: t_sp_arst_0_init_re -> ok Warning: Resizing cell port top.inst.i from 32 bits to 4 bits. Warning: Resizing cell port top.inst2.a from 32 bits to 4 bits. Warning: Resizing cell port top.inst1.a from 32 bits to 4 bits. Warning: No SAT model available for cell $auto$rename.cc:501:execute$73_gold (bb). Warning: No SAT model available for cell $auto$rename.cc:501:execute$74_gold (bb). Warning: No SAT model available for cell $auto$rename.cc:501:execute$75_gold (bb). Passed opt-opt_hier.tcl make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/opt' ...passed tests in tests/opt Passed techmap-buf.ys Passed various-abc9.ys Warning: reg '\QQQ' is assigned in a continuous assignment at < ok Passed various-abstract_init.ys Test: mem2reg -> ok Passed various-abstract_initstates.ys Warning: reg '\Q' is assigned in a continuous assignment at < ok Passed various-abstract_state.ys Test: mem2reg_bounds_tern -> ok Passed various-abstract_value.ys Warning: Feature 'write_aiger2' is experimental. Test: t_sp_arst_v_x_re -> ok Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2812_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2811_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2810_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2809_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2808_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2807_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2806_gold ($input_port). Warning: No SAT model available for cell $auto$rtlil_bufnorm.cc:108:bufNormalize$2805_gold ($input_port). Passed various-aiger2.ys Passed various-aiger_dff.ys Passed various-attrib05_port_conn.ys Passed ice40-ice40_opt.ys Passed microchip-widemux.ys Passed various-attrib07_func_call.ys [43]Passed various-autoname.ys Passed various-blackbox_wb.ys Test: t_sp_arst_v_0 -> ok Passed various-box_derive.ys Warning: Feature 'bufnorm' is experimental. Passed various-bufnorm_opt_clean.ys K[44]Passed various-bug1496.ys Passed various-bug1531.ys Passed various-bug1614.ys Passed various-bug1710.ys Test: mem_arst -> ok make -C tests/rtlil -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/rtlil' Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! < ok Passed rtlil-roundtrip-design.sh Passed various-bug2014.ys Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed various-bug3462.ys Warning: reg '\y' is assigned in a continuous assignment at < ok xprop_shl_4s3u_3: ok xprop_shl_4s3u_3: ok Passed various-bug3879.ys KTest: t_sp_arst_v_any -> ok Passed various-bug4082.ys Passed various-bug4865.ys Warning: Wire top.\y [11] is used but has no driver. Warning: Wire top.\y [10] is used but has no driver. Warning: Wire top.\y [9] is used but has no driver. Warning: Wire top.\y [8] is used but has no driver. Warning: Wire top.\y [7] is used but has no driver. Warning: Wire top.\y [6] is used but has no driver. Warning: Wire top.\y [5] is used but has no driver. Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [3] is used but has no driver. Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [2] is used but has no driver. Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [1] is used but has no driver. Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [0] is used but has no driver. Warning: Wire top.$delete_wire$14 is used but has no driver. Passed various-bug4909.ys Test: mem2reg -> ok xprop_shr_4u3u_3: ok xprop_shr_4u3u_3: ok Passed various-cellarray_array_connections.ys Passed various-check.ys Test: t_sp_arst_v_any_re -> ok make -C tests/verilog -f run-test.mk make[1]: Entering directory '/home/buildozer/aports/testing/yosys/src/tests/verilog' < ok Passed verilog-always_comb_latch_2.ys ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$< ok Passed verilog-always_comb_nolatch_2.ys Passed verilog-always_comb_nolatch_3.ys Passed verilog-always_comb_nolatch_4.ys Passed verilog-always_comb_nolatch_5.ys Passed verilog-always_comb_nolatch_6.ys Test: t_sp_arst_v_init_re -> ok Passed verilog-asgn_expr.ys < ok Passed verilog-assign_to_reg.ys Test: t_sp_arst_e_x -> ok Passed verilog-atom_type_signedness.ys < ok Warning: Wire TB.\rq_b [35] is used but has no driver. Warning: Wire TB.\rq_b [34] is used but has no driver. Warning: Wire TB.\rq_b [33] is used but has no driver. Warning: Wire TB.\rq_b [32] is used but has no driver. Warning: Wire TB.\rq_b [31] is used but has no driver. Warning: Wire TB.\rq_b [30] is used but has no driver. Warning: Wire TB.\rq_b [29] is used but has no driver. Warning: Wire TB.\rq_b [28] is used but has no driver. Warning: Wire TB.\rq_b [27] is used but has no driver. Warning: Wire TB.\rq_b [26] is used but has no driver. Warning: Wire TB.\rq_b [25] is used but has no driver. Warning: Wire TB.\rq_b [24] is used but has no driver. Warning: Wire TB.\rq_b [23] is used but has no driver. Warning: Wire TB.\rq_b [22] is used but has no driver. Warning: Wire TB.\rq_b [21] is used but has no driver. Warning: Wire TB.\rq_b [20] is used but has no driver. Warning: Wire TB.\rq_b [19] is used but has no driver. Warning: Wire TB.\rq_b [18] is used but has no driver. Warning: Wire TB.\rq_b [17] is used but has no driver. Warning: Wire TB.\rq_b [16] is used but has no driver. Warning: Wire TB.\rq_b [15] is used but has no driver. Warning: Wire TB.\rq_b [14] is used but has no driver. Warning: Wire TB.\rq_b [13] is used but has no driver. Warning: Wire TB.\rq_b [12] is used but has no driver. Warning: Wire TB.\rq_b [11] is used but has no driver. Warning: Wire TB.\rq_b [10] is used but has no driver. Warning: Wire TB.\rq_b [9] is used but has no driver. Warning: Wire TB.\rq_b [8] is used but has no driver. Warning: Wire TB.\rq_b [7] is used but has no driver. Warning: Wire TB.\rq_b [6] is used but has no driver. Warning: Wire TB.\rq_b [5] is used but has no driver. Warning: Wire TB.\rq_b [4] is used but has no driver. Warning: Wire TB.\rq_b [3] is used but has no driver. Warning: Wire TB.\rq_b [2] is used but has no driver. Warning: Wire TB.\rq_b [1] is used but has no driver. Warning: Wire TB.\rq_b [0] is used but has no driver. < ok Passed verilog-bug2037.ys < ok Test: t_sp_arst_e_any -> ok Passed verilog-bug5572.ys Passed xilinx-bug1598.ys Passed verilog-bug656.ys < Y[0] wire \ripple [0] source: < ok Passed verilog-const_arst.ys Warning: Complex async reset for dff `\q'. Warning: Resizing cell port TB.uut.data_out from 8 bits to 32 bits. Warning: Resizing cell port TB.uut.address_in_r from 10 bits to 8 bits. Passed various-celledges_shift.ys Warning: found logic loop in module pingpong: cell $memrd$\mem$< DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[2] wire \y1 [2] source: < DATA[3] wire \y2 [3] source: < DATA[2] wire \y1 [2] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[3] wire \y1 [3] source: < DATA[3] wire \y2 [3] source: < DATA[3] wire \y1 [3] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[2] wire \y2 [2] source: < DATA[0] wire \y1 [0] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[3] wire \y2 [3] source: < DATA[1] wire \y1 [1] source: < DATA[2] wire \y2 [2] source: < DATA[0] wire \y1 [0] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[2] wire \y1 [2] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[2] wire \y1 [2] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[3] wire \y1 [3] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[3] wire \y1 [3] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[0] wire \y1 [0] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[7] wire \y2 [3] source: < RD_DATA[1] wire \y1 [1] source: < RD_DATA[6] wire \y2 [2] source: < RD_DATA[0] wire \y1 [0] source: < DATA[0] wire \data [0] source: < Y[0] ERROR: Found 1 problems in 'check -assert'. Expected error pattern 'Found [0-9]+ problems in 'check -assert'' found !!! Passed various-check_4.ys Warning: wire '\a_q' is assigned in a block at < ok Passed verilog-delay_time_scale.ys Test: t_sp_arst_e_init -> ok Passed various-const_arg_loop.ys Passed verilog-doubleslash.ys Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. xprop_sshl_4u3u_3: ok xprop_sshl_4u3u_3: ok Passed verilog-fcall_smoke.ys < ok Warning: Drivers conflicting with a constant 1'1 driver: module input A[0] Warning: Drivers conflicting with a constant 1'1 driver: port Y[0] of cell some_buffer (buffer) Warning: reg '\Q' is assigned in a continuous assignment at < ok Passed qlf_k6n10f-mux.ys Passed various-deminout_unused.ys Passed various-design.ys ERROR: No saved design 'foo' found! Expected error pattern 'No saved design 'foo' found!' found !!! Passed various-design1.ys ERROR: No saved design 'foo' found! Expected error pattern 'No saved design 'foo' found!' found !!! xprop_sshr_4u3u_3: ok xprop_sshr_4u3u_3: ok Passed various-design2.ys ERROR: Second design missing module top_renamed. Expected error pattern 'Second design missing module top_renamed' found !!! Passed various-design_equal_fail.ys Passed various-design_equal_pass.ys Test: module_scope -> ok Passed ice40-latches.ys elab_sys_tasks.sv:8: Warning: X is 1. elab_sys_tasks.sv:22: Warning: Passed various-elab_sys_tasks.ys < ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed ice40-mul.ys Test: t_sp_arst_n_0 -> ok Passed ice40-rom.ys Passed techmap-booth.ys Passed ice40-shifter.ys Passed techmap-bug2332.ys Test: memory -> ok Test: module_scope_case -> ok Passed techmap-bug2759.ys Test: t_sp_arst_n_0_re -> ok xprop_sshr_4s3u_3: ok xprop_sshr_4s3u_3: ok [49]Test: t_sp_arst_n_any -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Passed techmap-bug2972.ys KTest: module_scope_func -> ok Test: t_sp_arst_n_any_re -> ok Passed nexus-mul.ys ERROR: Can't open ABC output file `/tmp/yosys-abc-MjjhIP/output.blif'. Expected error pattern 'ABC' found !!! Passed techmap-bug5574.ys KPassed techmap-cellmatch.ys Passed techmap-cellname.ys Test: t_sp_arst_n_init -> ok Passed techmap-clkbufmap.ys xprop_shift_4u3u_3: ok xprop_shift_4u3u_3: ok Passed techmap-clockgate.ys xprop_shift_4s3u_3: ok xprop_shift_4s3u_3: ok Test: t_sp_arst_n_init_re -> ok Passed ice40-tribuf.ys < ok Passed techmap-constmap.ys Passed various-equiv_assume.ys xprop_shift_4u2s_8: ok xprop_shift_4u2s_8: ok K make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/fsm' ...passed tests in tests/fsm xprop_shift_4s2s_8: ok xprop_shift_4s2s_8: ok Passed various-equiv_make_make_assert.ys Warning: wire '\Q' is assigned in a block at < ok /home/buildozer/aports/testing/yosys/src/share/simcells.v:476: Warning: Yosys has only limited support for tri-state logic at the moment. Test: t_sp_srst_x_x_re -> ok Passed techmap-dffinit.ys Passed various-equiv_opt_multiclock.ys Passed various-equiv_opt_undef.ys ERROR: Command stdout did have a line matching given regex "giraffe". Expected error pattern 'stdout did have a line' found !!! Passed various-exec.ys Passed techmap-cmp2lcu.ys Passed verilog-genblk_case.ys xprop_shift_4u3s_3: ok xprop_shift_4u3s_3: ok Test: named_genblk -> ok Test: t_sp_srst_0_x -> ok Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff0 Passed various-fib.ys Passed ice40-spram.ys Passed techmap-dfflegalize_adlatch.ys Passed techmap-dfflegalize_adff.ys Test: named_genblk -> ok < ok Test: muxtree -> ok Test: t_sp_srst_0_x_re -> ok Test: nested_genblk_resolve -> ok Passed various-fib_tern.ys Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff0 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff0 Test: t_sp_srst_0_0 -> ok Test: multiplier -> ok Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff0 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff2 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff1 Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff0 Passed techmap-dfflegalize_adlatch_init.ys Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff3 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff0 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff2 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff1 Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff0 Passed techmap-dfflegalize_adff_init.ys Test: nested_genblk_resolve -> ok Passed techmap-dfflegalize_aldff.ys Test: omsp_dbg_uart -> ok Warning: found logic loop in module self_rs_fsm: cell $procdff$34 ($adff) source: < Q[0] wire \next_state [0] source: < Y[0] wire \reset source: < Q[1] wire \next_state [1] source: < Y[0] wire \reset source: < Q[2] wire \next_state [2] source: < Y[0] wire \reset source: < Q[3] wire \next_state [3] source: < Y[0] wire \reset source: < Q[4] wire \next_state [4] source: < Y[0] wire \reset source: < Q[5] wire \next_state [5] source: < Y[0] wire \reset source: < Q[6] wire \next_state [6] source: < Y[0] wire \reset source: < Q[7] wire \next_state [7] source: < Y[0] wire \reset source: < Q[0] wire \reset_test [0] source: < Y[0] cell $logic_or$< Q[1] wire \reset_test [1] source: < Y[0] cell $logic_or$< ok Passed various-fsm-arst.ys Passed techmap-dfflegalize_aldff_init.ys Passed various-formalff_declockgate.ys Test: omsp_dbg_uart -> ok genblk_wire.sv:17: Warning: Identifier `\genblk1[0].x' is implicitly declared. genblk_wire.sv:17: Warning: Identifier `\genblk1[1].x' is implicitly declared. Passed verilog-genblk_wire.ys Passed nexus-mux.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nexus' ...passed tests in tests/arch/nexus xprop_shift_4s3s_3: ok xprop_shift_4s3s_3: ok Test: memory -> ok Test: t_sp_srst_0_any -> ok Passed various-func_port_implied_dir.ys Warning: Complex async reset for dff `\Q'. Passed ice40-macc.ys Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff4 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff0 Test: t_sp_srst_0_any_re -> ok Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff4 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff0 Passed techmap-dfflegalize_dffsr.ys xprop_shiftx_4u2s_8: ok xprop_shiftx_4u2s_8: ok Passed techmap-dfflegalize_dff.ys < ok Passed various-gen_if_null.ys Test: t_sp_srst_0_init -> ok Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Test: t_sp_srst_0_init_re -> ok xprop_shiftx_4u3s_3: ok xprop_shiftx_4u3s_3: ok xprop_mux_1: ok xprop_mux_1: ok Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff4 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff4 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff1 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff2 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff3 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff0 Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff0 Test: t_sp_srst_v_x -> ok Test: param_attr -> ok < ok Passed various-global_scope.ys Test: t_sp_srst_v_x_re -> ok Warning: Drivers conflicting with a constant 1'0 driver: module input PORT_A1_WR_BE_i[1] module input PORT_A1_WR_DATA_i[17] module input PORT_B1_WR_BE_i[1] module input PORT_B1_WR_DATA_i[17] Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff0 [$_DFFSR_PPP_]. Passed techmap-dfflegalize_dff_init.ys xprop_mux_3: ok xprop_mux_3: ok Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff0 [$_DFFSR_PPP_]. Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff4 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff4 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff0 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff3 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff2 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff1 Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff0 Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff0 [$_DFFSR_PPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff4 [$_DFFSRE_NPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff3 [$_DFFSRE_PNPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff2 [$_DFFSRE_PPNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff1 [$_DFFSRE_PPPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff0 [$_DFFSRE_PPPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff3 [$_DFFSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff2 [$_DFFSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff1 [$_DFFSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff0 [$_DFFSR_PPP_]. Test: t_sp_srst_v_0 -> ok Passed techmap-dfflegalize_dffsr_init.ys Warning: Resizing cell port cas.$mul$< ok Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff0 [$_DLATCHSR_PPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff0 [$_DLATCHSR_PPP_]. Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff3 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff2 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff1 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff0 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff3 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff2 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff1 Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff0 Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff0 [$_DLATCHSR_PPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff3 [$_DLATCHSR_NPP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff2 [$_DLATCHSR_PNP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff1 [$_DLATCHSR_PPN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff0 [$_DLATCHSR_PPP_]. Passed techmap-dfflegalize_dlatchsr_init.ys Test: t_sp_srst_v_any -> ok xprop_bmux_1_2: ok xprop_bmux_1_2: ok Passed techmap-dfflegalize_inv.ys Passed xilinx-dsp_fastfir.ys Passed techmap-dfflegalize_mince.ys Passed techmap-dfflegalize_minsrst.ys Passed techmap-dfflegalize_sr.ys Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff0 [$_SR_PP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff0 [$_SR_PP_]. Test: t_sp_srst_v_any_re -> ok Test: paramods -> ok Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff0 [$_SR_PP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff2 [$_SR_NP_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff1 [$_SR_PN_]. Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff0 [$_SR_PP_]. Passed ice40-mux.ys Passed techmap-dfflegalize_sr_init.ys Warning: Complex async reset for dff `\Q'. Passed techmap-dfflibmap.ys Passed ice40-bug1644.ys Warning: wire '\Q' is assigned in a block at < ok Warning: Shift register inference not yet supported for family xc3se. Passed techmap-extractinv.ys < ok Passed techmap-iopadmap.ys Passed techmap-lut2bmux.ys Passed techmap-lut2mux.ys Passed techmap-module_not_derived.ys Passed techmap-pmux2mux.ys Test: t_sp_srst_v_any_ce_gated -> ok xprop_bmux_2_2: ok xprop_bmux_2_2: ok Passed verilog-genvar_loop_decl_1.ys Test: process -> ok Passed techmap-techmap_replace.ys Passed techmap-techmap_chtype.ys xprop_bmux_3_1: ok xprop_bmux_3_1: ok Test: t_sp_srst_v_init -> ok Passed techmap-shiftx2mux.ys Test: operators -> ok Passed techmap-wireinit.ys Test: t_sp_srst_v_init_re -> ok Passed qlf_k6n10f-meminit.ys Passed verilog-genvar_loop_decl_2.ys Test: t_sp_srst_e_x -> ok Passed techmap-zinit.ys xprop_demux_1_2: ok xprop_demux_1_2: ok Test: t_sp_srst_e_x_re -> ok Passed techmap-han-carlson.tcl Test: t_sp_srst_e_0 -> ok Test: realexpr -> ok Passed techmap-kogge-stone.tcl Passed various-help.ys xprop_demux_2_2: ok xprop_demux_2_2: ok Test: t_sp_srst_e_0_re -> ok Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21. Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21. Passed verilog-genvar_loop_decl_3.ys Passed techmap-sklansky.tcl Warning: Shift register inference not yet supported for family xc3se. Test: process -> ok Passed techmap-bug5495.sh Test: t_sp_srst_e_any -> ok Test: realexpr -> ok Passed xilinx-dsp_simd.ys xprop_demux_3_1: ok xprop_demux_3_1: ok < ok Passed verilog-global_parameter.ys Passed various-hierarchy_defer.ys Passed techmap-recursive_runtest.sh Passed xilinx-logic.ys Passed techmap-mem_simple_4x1_runtest.sh make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/techmap' ...passed tests in tests/techmap < ok Test: repwhile -> ok Test: t_sp_srst_e_init -> ok Passed xilinx-opt_lut_ins.ys xprop_pmux_1_4: ok xprop_pmux_1_4: ok Test: t_sp_srst_e_init_re -> ok Passed verilog-ifdef_nest.ys Test: retime -> ok Test: repwhile -> ok Passed various-hierarchy_param.ys Test: t_sp_srst_n_x_re -> ok Test: t_sp_srst_n_x -> ok xprop_pmux_2_2: ok xprop_pmux_2_2: ok ERROR: Unterminated preprocessor conditional! Expected error pattern 'Unterminated preprocessor conditional!' found !!! Passed verilog-ifdef_unterminated.ys xprop_pmux_3_1: ok xprop_pmux_3_1: ok Passed xilinx-adffs.ys Test: retime -> ok < ok /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: t_sp_srst_n_0_re -> ok xprop_pmux_4_4: ok xprop_pmux_4_4: ok Test: scopes -> ok Test: sign_part_assign -> ok Test: t_sp_srst_n_any -> ok Passed microchip-dff.ys < ok Test: t_sp_srst_n_init -> ok attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033" Passed various-json_escape_chars.ys Passed verilog-incdec.ys Test: t_sp_srst_n_init_re -> ok xprop_bwmux_1: ok xprop_bwmux_1: ok Test: t_sp_srst_gv_x -> ok Passed various-ice40_mince_abc9.ys Warning: Resizing cell port top.u3.out from 1 bits to 2 bits. Passed various-json_scopeinfo.ys xprop_bweqx_1: ok xprop_bweqx_1: ok Passed verilog-include_self.ys xprop_bwmux_3: ok xprop_bwmux_3: ok Passed xilinx-fsm.ys Test: t_sp_srst_gv_x_re -> ok Passed xilinx-xilinx_dsp.ys xprop_bweqx_3: ok xprop_bweqx_3: ok Passed various-keep_hierarchy.ys Passed verilog-int_types.ys Test: signed_full_slice -> ok Test: t_sp_srst_gv_0 -> ok Test: scopes -> ok Passed various-lcov.ys Passed nanoxplore-latches.ys < ok Passed xilinx-xilinx_srl.ys Test: t_sp_srst_gv_0_re -> ok ERROR: Identifier `\b' is implicitly declared. Expected error pattern 'is implicitly declared.' found !!! Passed various-logger_error.ys Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. xprop_ff_1: ok xprop_ff_1: ok Test: sign_part_assign -> ok Warning: Ignoring boxed module $paramod\FDRE\INIT=1'0_$abc9_flop. Warning: Selection "asym_ram_sdp_read_wider" did not match any module. Test: rotate -> ok Test: t_sp_srst_gv_any -> ok Passed various-logger_nowarning.ys xprop_ff_3: ok xprop_ff_3: ok Test: signedexpr -> ok Test: t_sp_srst_gv_any_re -> ok Warning: Found log message matching -W regex: Added regex 'Successfully finished Verilog frontend.' to expected warning messages list. < ok < ok xprop_dff_1pd: ok xprop_dff_1pd: ok < ok Passed various-logic_param_simple.ys Test: t_sp_srst_gv_any_ce -> ok xprop_dff_1nd: ok xprop_dff_1nd: ok Test: string_format -> ok Passed verilog-macro_arg_tromp.ys Passed various-mem2reg.ys Test: string_format -> ok Test: t_sp_srst_gv_any_ce_gated -> ok Test: t_sp_srst_gv_init -> ok Test: subbytes -> ok Passed xilinx-dsp_abc9.ys Test: t_sp_srst_gv_init_re -> ok Passed xilinx-mul.ys ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';' Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!! Passed verilog-macro_unapplied.ys Passed various-memory_word_as_index.ys xprop_dff_3pd: ok xprop_dff_3pd: ok Test: t_wren_a4d4_NO_BYTE -> ok xprop_dff_3nd: ok xprop_dff_3nd: ok Test: sincos -> ok /home/buildozer/aports/testing/yosys/src/share/simcells.v:476: Warning: Yosys has only limited support for tri-state logic at the moment. Test: undef_eqx_nex -> ok ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a' Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!! Passed verilog-macro_unapplied_newline.ys Test: t_wren_a5d4_NO_BYTE -> ok Test: t_wren_a6d4_NO_BYTE -> ok /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /home/buildozer/aports/testing/yosys/src/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. xprop_dffe_1pnd: ok xprop_dffe_1pnd: ok Test: subbytes -> ok Test: t_wren_a3d8_NO_BYTE -> ok Test: usb_phy_tests -> ok Test: t_wren_a4d8_NO_BYTE -> ok Test: partsel -> ok Passed xilinx-xilinx_dffopt.ys < ok Test: t_wren_a4d4_W4_B4 -> ok Passed various-param_struct.ys Test: undef_eqx_nex -> ok Passed verilog-net_types.ys Test: sincos -> ok Test: task_func -> ok Test: t_wren_a4d8_W4_B4_separate -> ok xprop_dffe_1nnd: ok xprop_dffe_1nnd: ok < ok Passed various-peepopt.ys Test: rotate -> ok Test: verilog_primitives -> ok Passed verilog-package_task_func.ys Passed verilog-param_default.ys xprop_dffe_3pnd: ok xprop_dffe_3pnd: ok Passed various-pmux2shiftx.ys Test: usb_phy_tests -> ok Test: t_wren_a4d8_W8_B4_separate -> ok Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits. Warning: Resizing cell port act.os2.out from 3 bits to 2 bits. Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits. Warning: Resizing cell port act.os1.out from 3 bits to 1 bits. Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits. Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits. Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits. Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits. Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits. Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits. Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits. Passed xilinx-tribuf.ys Passed various-primitives.ys Passed various-port_sign_extend.ys Passed various-rand_const.ys Test: values -> ok Passed various-printattr.ys Passed verilog-param_int_types.ys Test: t_wren_a4d8_W8_B8 -> ok Test: t_wren_a4d8_W8_B8_separate -> ok Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21. Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18. Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22. Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16. Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17. Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70 Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68 Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63 Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61 Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58 Passed various-reg_wire_error.ys Test: t_wren_a4d2w8_W16_B4 -> ok Passed xilinx-pmgen_xilinx_srl.ys Passed verilog-param_no_default.ys xprop_dffe_1ppd: ok xprop_dffe_1ppd: ok Passed various-rename_scramble_name.ys Test: t_wren_a4d2w8_W16_B4_separate -> ok Test: t_wren_a4d4w4_W16_B4 -> ok < ok Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. Test: values -> ok xprop_dffe_1npd: ok xprop_dffe_1npd: ok Warning: Wire top.\_e is used but has no driver. Passed various-rename_unescape.ys Test: t_wren_a4d4w4_W16_B4_separate -> ok < ok Passed various-rename_wire_move_to_cell.ys Passed various-rtlil_signed_attribute.ys < ok Test: t_wren_a5d4w2_W16_B4_separate -> ok Passed various-rtlil_z_bits.ys Passed verilog-parameters_across_files.ys Test: vloghammer -> ok Test: case_expr_extend -> ok Test: wandwor -> ok Passed various-scopeinfo.ys Test: t_wren_a5d4w4_W16_B4 -> ok Test: case_expr_query -> ok Passed various-scratchpad.ys Passed verilog-past_signedness.ys Test: vloghammer -> ok Test: wandwor -> ok Passed xilinx-mul_unsigned.ys Passed various-script.ys Passed verilog-port_int_types.ys Passed verilog-prefix.ys Test: t_wren_a5d4w4_W16_B4_separate -> ok Test: t_wren_a4d8w2_W16_B4 -> ok Test: t_wren_a4d8w2_W16_B4_separate -> ok Test: t_wren_a5d8w1_W16_B4 -> ok { "creator": "Yosys 0.62 (git sha1 7326bb7d6641500ecb285c291a54a662cb1e76cf, g++ 15.2.0 -Os -fstack-clash-protection -fno-plt -fPIC -O3)", "modules": { "top": { "attributes": { "keep": "00000000000000000000000000000001", "top": "00000000000000000000000000000001", "src": "setundef.sv:5.1-10.10" }, "ports": { "o": { "direction": "output", "bits": [ "0", "0" ] } }, "cells": { "$assert$setundef.sv:8$2": { "hide_name": 1, "type": "$assert", "parameters": { }, "attributes": { "keep": "00000000000000000000000000000001", "src": "setundef.sv:8.3-8.21" }, "port_directions": { "A": "input", "EN": "input" }, "connections": { "A": [ "1" ], "EN": [ "1" ] } }, "$auto$chformal.cc:428:execute$6": { "hide_name": 1, "type": "$not", "parameters": { "A_SIGNED": "00000000000000000000000000000000", "A_WIDTH": "00000000000000000000000000000001", "Y_WIDTH": "00000000000000000000000000000001" }, "attributes": { }, "port_directions": { "A": "input", "Y": "output" }, "connections": { "A": [ "1" ], "Y": [ 2 ] } }, "$auto$chformal.cc:430:execute$8": { "hide_name": 1, "type": "$and", "parameters": { "A_SIGNED": "00000000000000000000000000000000", "A_WIDTH": "00000000000000000000000000000001", "B_SIGNED": "00000000000000000000000000000000", "B_WIDTH": "00000000000000000000000000000001", "Y_WIDTH": "00000000000000000000000000000001" }, "attributes": { }, "port_directions": { "A": "input", "B": "input", "Y": "output" }, "connections": { "A": [ 2 ], "B": [ "1" ], "Y": [ 3 ] } }, "foo": { "hide_name": 0, "type": "$scopeinfo", "parameters": { "TYPE": "module" }, "attributes": { "cell_module_not_derived": "00000000000000000000000000000001", "cell_src": "setundef.sv:6.15-6.21", "module": "$paramod\\foo\\a=2'00", "module_hdlname": "foo", "module_src": "setundef.sv:1.1-3.10" }, "port_directions": { }, "connections": { } } }, "netnames": { "$assert$setundef.sv:8$2_EN": { "hide_name": 1, "bits": [ "1" ], "attributes": { "src": "setundef.sv:8.3-8.21" } }, "$auto$rtlil.cc:3337:Not$7": { "hide_name": 1, "bits": [ 2 ], "attributes": { } }, "$auto$rtlil.cc:3384:And$9": { "hide_name": 1, "bits": [ 3 ], "attributes": { } }, "$eq$setundef.sv:8$3_Y": { "hide_name": 1, "bits": [ "1" ], "attributes": { "src": "setundef.sv:8.10-8.20" } }, "foo.o": { "hide_name": 0, "bits": [ "0", "0" ], "attributes": { "hdlname": "foo o", "src": "setundef.sv:1.47-1.48" } }, "o": { "hide_name": 0, "bits": [ "0", "0" ], "attributes": { "src": "setundef.sv:5.25-5.26" } } } } } } Passed various-setundef.ys Test: arrays03 -> ok Test: implicit_ports -> ok Test: wreduce -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/simple' ...passed tests in tests/simple Test: defvalue -> ok Test: t_wren_a5d8w1_W16_B4_separate -> ok Passed various-sformatf.ys Test: t_wren_a5d8w2_W16_B4_separate -> ok Warning: Module top contains RTLIL processes with sync rules. Such RTLIL processes can't always be mapped directly to Verilog always blocks. unintended changes in simulation behavior are possible! Use "proc" to convert processes to logic networks and registers. Passed verilog-reset_auto_counter.ys Test: t_wren_a5d8w2_W16_B4 -> ok Passed verilog-roundtrip_proc.ys Test: t_wren_a4d16w1_W16_B4 -> ok < ok Passed various-shregmap.ys Passed verilog-priority_if_enc.ys Test: lesser_size_cast -> ok Passed xilinx-macc.ys Passed verilog-sign_array_query.ys Test: matching_end_labels -> ok Passed various-sim_const.ys Passed various-splitnets.ys specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string. specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string. specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string. Test: t_wren_a4d4w2_W8_B8 -> ok Warning: No SAT model available for cell B_0 ($specrule). Warning: No SAT model available for cell C_0 ($specrule). Warning: No SAT model available for cell A_0 ($specify3). Warning: No SAT model available for cell A_0 ($specify2). Warning: No SAT model available for cell B_0 ($specify2). Test: memwr_port_connection -> ok Test: t_wren_a4d16w1_W16_B4_separate -> ok Warning: wire '\o' is assigned in a block at < ok Passed various-stat.ys Passed various-stat_high_level.ys Passed various-stat_hierarchy.ys Passed various-stat_high_level2.ys Passed verilog-sva-in-case-expr.ys Test: t_wren_a4d4w1_W8_B8_separate -> ok Passed verilog-size_cast.ys Test: t_wren_a4d4w1_W8_B8 -> ok < ok Passed various-struct_access.ys Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports. Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports. Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports. Passed various-submod_extract.ys Passed various-submod.ys Test: t_wren_a4d8w2_W8_B8 -> ok Passed verilog-typedef_across_files.ys Passed verilog-typedef_const_shadow.ys Passed various-sv_defines.ys ERROR: Duplicate macro arguments with name `x'. Expected error pattern 'Duplicate macro arguments with name `x'' found !!! Passed various-sv_defines_dup.ys Test: t_wren_a4d8w2_W8_B8_separate -> ok Test: t_wren_a3d8w2_W8_B8 -> ok Passed verilog-typedef_legacy_conflict.ys unbased_unsized.sv:21: Warning: Yosys has only limited support for tri-state logic at the moment. ERROR: Mismatched brackets in macro argument: [ and }. Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!! Passed various-sv_defines_mismatch.ys Test: t_wren_a3d8w2_W8_B8_separate -> ok Test: t_wren_a4d4w2_W8_B4 -> ok Warning: Resizing cell port top.pt.inp from 32 bits to 64 bits. ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default). Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!! Passed verilog-unbased_unsized.ys Passed various-sv_defines_too_few.ys Test: t_wren_a4d4w2_W8_B4_separate -> ok Passed verilog-unbased_unsized_shift.ys Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits. Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits. Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits. Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits. Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits. Test: t_wren_a4d2w4_W8_B4 -> ok Passed various-tcl_apis.ys Test: t_wren_a4d4w4_W8_B4_separate -> ok Passed various-wrapcell.ys Test: t_wren_a4d2w4_W8_B4_separate -> ok Test: t_wren_a4d4w4_W8_B4 -> ok Test: t_wren_a4d4w4_W4_B4_separate -> ok Test: t_wren_a4d4w4_W4_B4 -> ok Passed various-wreduce2.ys Passed various-wreduce.ys Test: t_wren_a4d4w5_W4_B4 -> ok Test: wreduce -> ok Passed various-write_gzip.ys Passed verilog-unique_if.ys < ok Test: t_geom_a5d32_wren -> ok Passed verilog-unique0_if_enc.ys Test: t_wren_a4d4w5_W4_B4_separate -> ok Passed verilog-unbased_unsized_tern.ys Test: t_geom_a6d16_wren -> ok Passed various-timeest.ys Passed various-logger_cmd_error.sh Test: t_geom_a5d64_wren -> ok ERROR: Found `else outside of macro conditional branch! Expected error pattern 'Found `else outside of macro conditional branch!' found !!! Passed verilog-unmatched_else.ys Test: t_geom_a6d30_wren -> ok Passed various-chparam.sh Passed various-hierarchy.sh Passed verilog-unique_if_enc.ys ERROR: Found `elsif outside of macro conditional branch! Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!! ERROR: Found `endif outside of macro conditional branch! Expected error pattern 'Found `endif outside of macro conditional branch!' found !!! Passed verilog-unmatched_elsif.ys Passed verilog-unmatched_endif.ys Passed various-clk2fflogic_effects.sh ERROR: Found `endif outside of macro conditional branch! Expected error pattern 'Found `endif outside of macro conditional branch!' found !!! < ok Passed xilinx-mux_lut4.ys Test: t_geom_a7d6_wren -> ok Passed verilog-unreachable_case_sign.ys Test: t_geom_a6d64_wren -> ok Passed verilog-upto.ys Test: macro_arg_spaces -> ok Warning: wire '\b' is assigned in a block at < ok Warning: wire '\wire_1' is assigned in a block at wire_and_var.sv:21.41-21.51. Warning: reg '\reg_2' is assigned in a continuous assignment at wire_and_var.sv:22.57-22.66. Warning: reg '\var_reg_2' is assigned in a continuous assignment at wire_and_var.sv:26.77-26.90. Warning: wire '\wire_logic_1' is assigned in a block at wire_and_var.sv:30.65-30.81. Warning: wire '\wire_integer_1' is assigned in a block at wire_and_var.sv:31.73-31.91. Passed verilog-void_func.ys Passed verilog-wire_and_var.ys Test: t_geom_a7d17_wren -> ok Passed various-svalways.sh Test: t_geom_a8d4_wren -> ok Test: asgn_binop -> ok Test: t_geom_a8d6_wren -> ok Test: t_geom_a9d4_wren -> ok Test: t_geom_a9d8_wren -> ok Passed verilog-local_include.sh Passed various-sv_implicit_ports.sh Passed various-async.sh Passed various-pmgen_reduce.ys Test: t_geom_a9d5_wren -> ok Test: t_geom_a3d18_9b1B -> ok Test: t_geom_a4d4_9b1B -> ok Test: t_geom_a9d6_wren -> ok Passed xilinx-nosrl.ys Test: t_geom_a4d18_9b1B -> ok Test: t_geom_a6d4_9b1B -> ok Test: t_geom_a5d32_9b1B -> ok Test: t_geom_a7d11_9b1B -> ok Test: t_geom_a7d18_9b1B -> ok Test: t_geom_a11d1_9b1B -> ok Test: t_wide_sdp_a8r1w1b1x1 -> ok Test: t_wide_sdp_a6r1w1b1x1 -> ok Test: t_wide_sdp_a7r1w1b1x1 -> ok Test: t_wide_sdp_a6r3w0b0x0 -> ok Test: t_wide_sdp_a6r0w0b0x0 -> ok Test: t_wide_sdp_a6r1w0b0x0 -> ok Test: t_wide_sdp_a6r2w0b0x0 -> ok Test: t_wide_sdp_a6r4w0b0x0 -> ok Test: t_wide_sdp_a6r0w1b0x0 -> ok Test: t_wide_sdp_a6r5w0b0x0 -> ok Test: t_wide_sdp_a6r0w1b1x0 -> ok Test: t_wide_sdp_a6r0w2b0x0 -> ok Warning: Resizing cell port pipeline.$mul$< ok Passed verilog-func_upto.ys Test: t_wide_sdp_a6r0w3b2x0 -> ok Test: t_wide_sdp_a7r0w0b0x0 -> ok Test: t_wide_sdp_a7r1w0b0x0 -> ok Test: t_wide_sdp_a7r2w0b0x0 -> ok Test: t_wide_sdp_a6r0w4b2x0 -> ok Test: t_wide_sdp_a7r0w1b0x0 -> ok Test: t_wide_sdp_a7r3w0b0x0 -> ok Test: t_wide_sdp_a7r4w0b0x0 -> ok Test: t_wide_sdp_a7r0w1b1x0 -> ok Test: t_wide_sdp_a7r5w0b0x0 -> ok Test: t_wide_sdp_a7r0w2b0x0 -> ok Test: t_wide_sdp_a6r0w5b2x0 -> ok Test: t_wide_sdp_a7r0w2b2x0 -> ok Test: t_wide_sdp_a7r0w3b2x0 -> ok Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sp_mix_a6r1w1b1 -> ok Test: t_wide_sp_mix_a8r1w1b1 -> ok Test: t_wide_sp_mix_a7r1w1b1 -> ok Test: t_wide_sp_mix_a6r0w0b0 -> ok Test: t_wide_sp_mix_a6r1w0b0 -> ok Test: t_wide_sp_mix_a6r2w0b0 -> ok Test: t_wide_sp_mix_a6r3w0b0 -> ok Test: t_wide_sp_mix_a6r0w1b0 -> ok Test: t_wide_sdp_a7r0w5b2x0 -> ok Test: t_wide_sp_mix_a6r4w0b0 -> ok Test: t_wide_sp_mix_a6r0w2b0 -> ok Test: t_wide_sp_mix_a6r5w0b0 -> ok Test: t_wide_sp_mix_a6r0w1b1 -> ok Test: t_wide_sp_mix_a6r0w2b2 -> ok Test: t_wide_sp_mix_a6r0w3b2 -> ok Test: t_wide_sp_mix_a6r0w4b2 -> ok Test: t_wide_sp_mix_a7r0w0b0 -> ok Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_mix_a7r2w0b0 -> ok Test: t_wide_sp_mix_a7r3w0b0 -> ok Test: t_wide_sp_mix_a6r0w5b2 -> ok Test: t_wide_sp_mix_a7r0w1b0 -> ok Test: t_wide_sp_mix_a7r0w1b1 -> ok Test: t_wide_sp_mix_a7r0w2b0 -> ok Test: t_wide_sp_mix_a7r0w2b2 -> ok Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a7r4w0b0 -> ok Test: t_wide_sp_mix_a7r0w3b2 -> ok Test: t_wide_sp_tied_a6r1w1b1 -> ok Test: t_wide_sp_mix_a7r0w4b2 -> ok Test: t_wide_sp_tied_a7r1w1b1 -> ok Test: t_wide_sp_tied_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w0b0 -> ok Test: t_wide_sp_mix_a7r0w5b2 -> ok Test: t_wide_sp_tied_a6r1w0b0 -> ok Test: t_wide_sp_tied_a6r2w0b0 -> ok Test: t_wide_sp_tied_a6r3w0b0 -> ok Test: t_wide_sp_tied_a6r0w1b0 -> ok Test: t_wide_sp_tied_a6r4w0b0 -> ok Test: t_wide_sp_tied_a6r0w1b1 -> ok Test: t_wide_sp_tied_a6r0w2b0 -> ok Test: t_wide_sp_tied_a6r0w2b2 -> ok Test: t_wide_sp_tied_a6r5w0b0 -> ok Test: t_wide_sp_tied_a6r0w3b2 -> ok Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a7r1w0b0 -> ok Test: t_wide_sp_tied_a6r0w4b2 -> ok Test: t_wide_sp_tied_a7r2w0b0 -> ok Test: t_wide_sp_tied_a7r3w0b0 -> ok Passed xilinx-latches.ys Test: t_wide_sp_tied_a7r4w0b0 -> ok Test: t_wide_sp_tied_a7r0w1b0 -> ok Test: t_wide_sp_tied_a7r0w1b1 -> ok Test: t_wide_sp_tied_a6r0w5b2 -> ok Test: t_wide_sp_tied_a7r0w2b0 -> ok Test: t_wide_sp_tied_a7r0w2b2 -> ok Test: t_wide_sp_tied_a7r5w0b0 -> ok Test: t_wide_sp_tied_a7r0w3b2 -> ok Test: t_wide_read_a6r1w1b1 -> ok Test: t_wide_write_a6r1w1b1 -> ok Test: t_wide_read_a7r1w1b1 -> ok Passed various-plugin.sh Test: t_wide_write_a7r1w1b1 -> ok Test: t_wide_sp_tied_a7r0w4b2 -> ok Test: t_wide_read_a8r1w1b1 -> ok Test: t_wide_write_a8r1w1b1 -> ok Test: t_wide_read_a6r0w0b0 -> ok Test: t_wide_write_a6r0w0b0 -> ok Test: t_wide_read_a6r1w0b0 -> ok Test: t_wide_write_a6r1w0b0 -> ok Test: t_wide_sp_tied_a7r0w5b2 -> ok Test: t_wide_read_a6r2w0b0 -> ok Test: t_wide_write_a6r3w0b0 -> ok Test: t_wide_write_a6r2w0b0 -> ok Test: t_wide_read_a6r3w0b0 -> ok Test: t_wide_read_a6r4w0b0 -> ok Test: t_wide_write_a6r4w0b0 -> ok Test: t_wide_write_a6r0w1b0 -> ok Test: t_wide_read_a6r0w1b0 -> ok Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_read_a6r5w0b0 -> ok Test: t_wide_write_a6r0w1b1 -> ok Test: t_wide_write_a6r0w2b0 -> ok Test: t_wide_read_a6r0w2b0 -> ok Test: t_wide_write_a6r0w2b2 -> ok Test: t_wide_read_a6r0w2b2 -> ok Test: t_wide_write_a6r5w0b0 -> ok Passed qlf_k6n10f-ioff.ys Test: t_wide_write_a6r0w3b2 -> ok Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_read_a6r0w4b2 -> ok Test: t_wide_read_a7r0w0b0 -> ok Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_write_a7r0w0b0 -> ok Test: t_wide_read_a7r1w0b0 -> ok Test: t_wide_write_a7r1w0b0 -> ok Test: t_wide_read_a7r2w0b0 -> ok Test: t_wide_write_a7r2w0b0 -> ok Test: t_wide_write_a7r3w0b0 -> ok Test: t_wide_read_a7r3w0b0 -> ok Test: t_wide_read_a6r0w5b2 -> ok Test: t_wide_read_a7r4w0b0 -> ok Test: t_wide_write_a6r0w5b2 -> ok Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. Test: t_wide_write_a7r4w0b0 -> ok Test: t_wide_write_a7r0w1b1 -> ok Test: t_wide_read_a7r0w1b1 -> ok Test: t_wide_read_a7r0w1b0 -> ok Test: t_wide_read_a7r5w0b0 -> ok Test: t_wide_write_a7r0w1b0 -> ok Test: t_wide_read_a7r0w2b0 -> ok Passed xilinx-dffs.ys Passed xilinx-attributes_test.ys Test: t_wide_write_a7r0w2b0 -> ok Test: t_wide_read_a7r0w2b2 -> ok Test: t_wide_write_a7r5w0b0 -> ok Test: t_wide_read_a7r0w3b2 -> ok Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[0] --> Y[0] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[0] --> Q[0] wire \dword [0] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[0] --> Y[0] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[1] --> Y[1] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[1] --> Q[1] wire \dword [1] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[1] --> Y[1] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[2] --> Y[2] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[2] --> Q[2] wire \dword [2] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[2] --> Y[2] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[3] --> Y[3] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[3] --> Q[3] wire \dword [3] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[3] --> Y[3] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[4] --> Y[4] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[4] --> Q[4] wire \dword [4] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[4] --> Y[4] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[5] --> Y[5] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[5] --> Q[5] wire \dword [5] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[5] --> Y[5] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[6] --> Y[6] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[6] --> Q[6] wire \dword [6] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[6] --> Y[6] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[7] --> Y[7] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[7] --> Q[7] wire \dword [7] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[7] --> Y[7] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[8] --> Y[8] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[8] --> Q[8] wire \dword [8] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[8] --> Y[8] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[9] --> Y[9] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[9] --> Q[9] wire \dword [9] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[9] --> Y[9] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[10] --> Y[10] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[10] --> Q[10] wire \dword [10] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[10] --> Y[10] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[11] --> Y[11] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[11] --> Q[11] wire \dword [11] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[11] --> Y[11] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[12] --> Y[12] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[12] --> Q[12] wire \dword [12] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[12] --> Y[12] Test: t_wide_write_a7r0w3b2 -> ok Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[13] --> Y[13] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[13] --> Q[13] wire \dword [13] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[13] --> Y[13] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[14] --> Y[14] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[14] --> Q[14] wire \dword [14] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[14] --> Y[14] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[15] --> Y[15] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[15] --> Q[15] wire \dword [15] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[15] --> Y[15] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[16] --> Y[16] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[16] --> Q[16] wire \dword [16] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[16] --> Y[16] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[17] --> Y[17] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[17] --> Q[17] wire \dword [17] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[17] --> Y[17] Test: t_wide_write_a7r0w2b2 -> ok Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[18] --> Y[18] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[18] --> Q[18] wire \dword [18] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[18] --> Y[18] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[19] --> Y[19] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[19] --> Q[19] wire \dword [19] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[19] --> Y[19] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[20] --> Y[20] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[20] --> Q[20] wire \dword [20] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[20] --> Y[20] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[21] --> Y[21] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[21] --> Q[21] wire \dword [21] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[21] --> Y[21] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[22] --> Y[22] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[22] --> Q[22] wire \dword [22] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[22] --> Y[22] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[23] --> Y[23] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[23] --> Q[23] wire \dword [23] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[23] --> Y[23] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[24] --> Y[24] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[24] --> Q[24] wire \dword [24] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[24] --> Y[24] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[25] --> Y[25] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[25] --> Q[25] wire \dword [25] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[25] --> Y[25] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[26] --> Y[26] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[26] --> Q[26] wire \dword [26] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[26] --> Y[26] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[27] --> Y[27] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[27] --> Q[27] wire \dword [27] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[27] --> Y[27] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[28] --> Y[28] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[28] --> Q[28] wire \dword [28] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[28] --> Y[28] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[29] --> Y[29] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[29] --> Q[29] wire \dword [29] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[29] --> Y[29] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[30] --> Y[30] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[30] --> Q[30] wire \dword [30] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[30] --> Y[30] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[31] --> Y[31] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[31] --> Q[31] wire \dword [31] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[31] --> Y[31] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[32] --> Y[32] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[32] --> Q[32] wire \dword [32] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[32] --> Y[32] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[33] --> Y[33] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[33] --> Q[33] wire \dword [33] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[33] --> Y[33] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[34] --> Y[34] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[34] --> Q[34] wire \dword [34] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[34] --> Y[34] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[35] --> Y[35] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[35] --> Q[35] wire \dword [35] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[35] --> Y[35] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[36] --> Y[36] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[36] --> Q[36] wire \dword [36] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[36] --> Y[36] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[37] --> Y[37] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[37] --> Q[37] wire \dword [37] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[37] --> Y[37] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[38] --> Y[38] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[38] --> Q[38] wire \dword [38] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[38] --> Y[38] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[39] --> Y[39] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[39] --> Q[39] wire \dword [39] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[39] --> Y[39] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[40] --> Y[40] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[40] --> Q[40] wire \dword [40] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[40] --> Y[40] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[41] --> Y[41] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[41] --> Q[41] wire \dword [41] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[41] --> Y[41] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[42] --> Y[42] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[42] --> Q[42] wire \dword [42] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[42] --> Y[42] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[43] --> Y[43] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[43] --> Q[43] wire \dword [43] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[43] --> Y[43] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[44] --> Y[44] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[44] --> Q[44] wire \dword [44] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[44] --> Y[44] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[45] --> Y[45] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[45] --> Q[45] wire \dword [45] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[45] --> Y[45] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[46] --> Y[46] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[46] --> Q[46] wire \dword [46] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[46] --> Y[46] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[47] --> Y[47] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[47] --> Q[47] wire \dword [47] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[47] --> Y[47] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[48] --> Y[48] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[48] --> Q[48] wire \dword [48] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[48] --> Y[48] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[49] --> Y[49] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[49] --> Q[49] wire \dword [49] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[49] --> Y[49] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[50] --> Y[50] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[50] --> Q[50] wire \dword [50] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[50] --> Y[50] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[51] --> Y[51] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[51] --> Q[51] wire \dword [51] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[51] --> Y[51] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[52] --> Y[52] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[52] --> Q[52] wire \dword [52] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[52] --> Y[52] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[53] --> Y[53] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[53] --> Q[53] wire \dword [53] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[53] --> Y[53] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[54] --> Y[54] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[54] --> Q[54] wire \dword [54] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[54] --> Y[54] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[55] --> Y[55] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[55] --> Q[55] wire \dword [55] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[55] --> Y[55] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[56] --> Y[56] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[56] --> Q[56] wire \dword [56] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[56] --> Y[56] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[57] --> Y[57] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[57] --> Q[57] wire \dword [57] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[57] --> Y[57] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[58] --> Y[58] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[58] --> Q[58] wire \dword [58] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[58] --> Y[58] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[59] --> Y[59] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[59] --> Q[59] wire \dword [59] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[59] --> Y[59] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[60] --> Y[60] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[60] --> Q[60] wire \dword [60] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[60] --> Y[60] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[61] --> Y[61] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[61] --> Q[61] wire \dword [61] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[61] --> Y[61] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[62] --> Y[62] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[62] --> Q[62] wire \dword [62] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[62] --> Y[62] Warning: found logic loop in module latch_002_gate: cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48 A[63] --> Y[63] cell $auto$proc_dlatch.cc:432:proc_dlatch$13479 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13 D[63] --> Q[63] wire \dword [63] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27 cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40 A[63] --> Y[63] Test: t_wide_write_a7r0w4b2 -> ok Test: t_quad_port_a4d2 -> ok Test: t_quad_port_a2d2 -> ok Test: t_wide_read_a7r0w4b2 -> ok Test: t_quad_port_a5d2 -> ok Test: t_quad_port_a4d4 -> ok Test: t_wide_quad_a4w2r2 -> ok Test: t_wide_oct_a4w2r2 -> ok Test: t_wide_oct_a4w2r1 -> ok Test: t_wide_quad_a4w2r1 -> ok Test: t_wide_oct_a4w2r3 -> ok Test: t_wide_quad_a4w2r3 -> ok Test: t_quad_port_a4d8 -> ok Test: t_quad_port_a6d2 -> ok Test: t_wide_write_a7r0w5b2 -> ok Test: t_wide_quad_a4w2r4 -> ok Test: t_wide_read_a7r0w5b2 -> ok Test: t_wide_quad_a4w2r5 -> ok Test: t_wide_oct_a4w2r4 -> ok Test: t_wide_oct_a4w2r5 -> ok Test: t_wide_quad_a4w2r6 -> ok Test: t_wide_oct_a4w2r6 -> ok Test: t_wide_quad_a4w2r7 -> ok Test: t_wide_oct_a4w2r7 -> ok Test: t_wide_quad_a4w2r8 -> ok Test: t_wide_quad_a4w4r1 -> ok Test: t_wide_oct_a4w4r1 -> ok Test: t_wide_oct_a4w2r8 -> ok Test: t_wide_oct_a4w4r4 -> ok Test: t_wide_quad_a4w4r4 -> ok Test: t_wide_oct_a4w4r6 -> ok Test: t_wide_quad_a5w2r1 -> ok Test: t_wide_oct_a4w2r9 -> ok Test: t_wide_quad_a4w2r9 -> ok Test: t_wide_oct_a5w2r1 -> ok Test: t_wide_quad_a4w4r6 -> ok Test: t_wide_quad_a4w4r9 -> ok Test: t_wide_quad_a5w2r4 -> ok Test: t_wide_oct_a5w2r4 -> ok Test: t_wide_oct_a4w4r9 -> ok Test: t_wide_quad_a5w2r9 -> ok Test: t_wide_oct_a5w2r9 -> ok Test: t_no_reset -> ok Test: t_gclken -> ok Test: t_ungated -> ok Test: t_gclken_ce -> ok Test: t_rom_case_block -> ok Test: t_grden -> ok Test: t_rom_case -> ok Test: t_excl_rst -> ok Test: t_exclwr -> ok Test: t_trans_rst -> ok Test: t_wr_byte -> ok Test: t_transwr -> ok Test: t_trans_byte -> ok Test: t_wr_rst_byte -> ok Test: t_grden_ce -> ok Test: t_rdenrst_wr_byte -> ok Test: t_rst_wr_byte -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/memlib' ...passed tests in tests/memlib Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. Passed nanoxplore-adffs.ys Passed various-dynamic_part_select.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/various' ...passed tests in tests/various Passed xilinx-macc.sh Passed xilinx-tribuf.sh Passed nanoxplore-meminit.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. Passed xilinx-dsp_cascade.ys Passed nanoxplore-mux.ys Passed ecp5-memories.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ecp5' ...passed tests in tests/arch/ecp5 Passed xilinx-mux.ys Passed xilinx-asym_ram_sdp.ys Passed xilinx-abc9_dff.ys Warning: Resizing cell port TB.uut.address_in_w from 11 bits to 10 bits. Warning: Resizing cell port TB.uut.data_in from 18 bits to 36 bits. Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. Test: partsel -> ok make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/simple_abc9' ...passed tests in tests/simple_abc9 Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. Warning: Resizing cell port TB.uut.address_in_w from 10 bits to 8 bits. Warning: Resizing cell port TB.uut.data_in from 8 bits to 32 bits. Passed qlf_k6n10f-t_mem2.ys Passed nanoxplore-lutram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/nanoxplore' ...passed tests in tests/arch/nanoxplore Passed qlf_k6n10f-t_mem4.ys Passed qlf_k6n10f-t_mem3.ys Warning: Resizing cell port sp_read_or_write.mem.0.0.BWE_A from 8 bits to 9 bits. Warning: Resizing cell port sp_read_or_write.mem.0.0.BWE_B from 8 bits to 9 bits. Passed xilinx-priority_memory.ys Warning: Shift register inference not yet supported for family xc3s. Passed qlf_k6n10f-t_mem1.ys Passed qlf_k6n10f-t_mem6.ys Passed qlf_k6n10f-t_mem5.ys Passed xilinx-lutram.ys Passed verilog-dynamic_range_lhs.sh make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/verilog' ...passed tests in tests/verilog Warning: Resizing cell port TB.uut.data_out from 18 bits to 36 bits. Warning: Resizing cell port TB.uut.address_in_r from 11 bits to 10 bits. Passed qlf_k6n10f-t_mem0.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/quicklogic/qlf_k6n10f' ...passed tests in tests/arch/quicklogic/qlf_k6n10f Passed xilinx-blockram.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/xilinx' ...passed tests in tests/arch/xilinx Passed ice40-memories.ys make[1]: Leaving directory '/home/buildozer/aports/testing/yosys/src/tests/arch/ice40' ...passed tests in tests/arch/ice40 Passed "make test". rm tests/sdc/run-test.mk tests/sat/run-test.mk tests/arch/quicklogic/pp3/run-test.mk tests/arch/efinix/run-test.mk tests/arch/anlogic/run-test.mk tests/arch/microchip/run-test.mk tests/arch/ice40/run-test.mk tests/bugpoint/run-test.mk tests/arch/gowin/run-test.mk tests/arch/machxo2/run-test.mk tests/arch/quicklogic/qlf_k6n10f/run-test.mk tests/opt/run-test.mk tests/arch/intel_alm/run-test.mk tests/various/run-test.mk tests/arch/nanoxplore/run-test.mk tests/verilog/run-test.mk tests/arch/nexus/run-test.mk tests/rtlil/run-test.mk tests/sim/run-test.mk tests/arch/gatemate/run-test.mk tests/arch/ecp5/run-test.mk tests/svtypes/run-test.mk tests/arch/xilinx/run-test.mk tests/techmap/run-test.mk >>> yosys: Entering fakeroot... [Makefile.conf] CONFIG:=gcc [Makefile.conf] PREFIX:=/usr [Makefile.conf] ABCEXTERNAL:=/usr/bin/abc [Makefile.conf] BOOST_PYTHON_LIB:=-lpython3.12 -lboost_python312 [Makefile.conf] ENABLE_ABC:=1 [Makefile.conf] ENABLE_LIBYOSYS:=1 [Makefile.conf] ENABLE_NDEBUG:=1 [Makefile.conf] ENABLE_PROTOBUF:=1 [Makefile.conf] ENABLE_PYOSYS:=1 [Makefile.conf] PYOSYS_USE_UV:=0 mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc yosys-witness /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin if [ -n "strip" ]; then strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys; fi if [ -n "strip" ]; then strip /home/buildozer/aports/testing/yosys/pkg/yosys/usr/bin/yosys-filterlib; fi mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys cp -r share/. /home/buildozer/aports/testing/yosys/pkg/yosys/usr/share/yosys/. mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/ if [ -n "strip" ]; then strip -S /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/yosys/libyosys.so; fi mkdir -p /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys cp .//pyosys/__init__.py /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/__init__.py cp libyosys.so /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/libyosys.so cp -r share /home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys '/home/buildozer/aports/testing/yosys/pkg/yosys/usr/lib/python3.12/site-packages/pyosys/libyosys.so' -> '/usr/lib/yosys/libyosys.so' >>> yosys-dev*: Running split function dev... 'usr/bin/yosys-config' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/usr/bin/yosys-config' './usr/share/yosys/include' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/./usr/share/yosys/include' './usr/lib/python3.12/site-packages/pyosys/share/include' -> '/home/buildozer/aports/testing/yosys/pkg/yosys-dev/./usr/lib/python3.12/site-packages/pyosys/share/include' >>> yosys-dev*: Preparing subpackage yosys-dev... >>> yosys-dev*: Stripping binaries >>> yosys-dev*: Running postcheck for yosys-dev >>> py3-yosys*: Running split function py3... 'usr/lib/python3.12' -> '/home/buildozer/aports/testing/yosys/pkg/py3-yosys/usr/lib/python3.12' >>> py3-yosys*: Preparing subpackage py3-yosys... >>> py3-yosys*: Running postcheck for py3-yosys >>> yosys*: Running postcheck for yosys >>> yosys*: Preparing package yosys... >>> yosys*: Stripping binaries >>> yosys*: Scanning shared objects >>> yosys-dev*: Scanning shared objects >>> py3-yosys*: Tracing dependencies... python3 yosys=0.62-r0 python3~3.12 yosys=0.62-r0 >>> py3-yosys*: Package size: 9.1 MB >>> py3-yosys*: Compressing data... >>> py3-yosys*: Create checksum... >>> py3-yosys*: Create py3-yosys-0.62-r0.apk >>> yosys-dev*: Tracing dependencies... python3~3.12 >>> yosys-dev*: Package size: 1.2 MB >>> yosys-dev*: Compressing data... >>> yosys-dev*: Create checksum... >>> yosys-dev*: Create yosys-dev-0.62-r0.apk >>> yosys*: Tracing dependencies... abc so:libc.musl-x86_64.so.1 so:libffi.so.8 so:libgcc_s.so.1 so:libpython3.12.so.1.0 so:libreadline.so.8 so:libstdc++.so.6 so:libtcl8.6.so so:libz.so.1 >>> yosys*: Package size: 66.9 MB >>> yosys*: Compressing data... >>> yosys*: Create checksum... >>> yosys*: Create yosys-0.62-r0.apk >>> yosys: Build complete at Mon, 09 Feb 2026 15:26:03 +0000 elapsed time 0h 11m 13s >>> yosys: Cleaning up srcdir >>> yosys: Cleaning up pkgdir >>> yosys: Cleaning up tmpdir >>> yosys: Uninstalling dependencies... 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abseil-cpp-kernel-timeout-internal (20250814.1-r0) (216/360) Purging abseil-cpp-log-internal-check-op (20250814.1-r0) (217/360) Purging abseil-cpp-leak-check (20250814.1-r0) (218/360) Purging abseil-cpp-log-initialize (20250814.1-r0) (219/360) Purging abseil-cpp-log-internal-globals (20250814.1-r0) (220/360) Purging abseil-cpp-log-internal-nullguard (20250814.1-r0) (221/360) Purging abseil-cpp-log-internal-structured-proto (20250814.1-r0) (222/360) Purging abseil-cpp-log-internal-proto (20250814.1-r0) (223/360) Purging abseil-cpp-log-sink (20250814.1-r0) (224/360) Purging abseil-cpp-random-internal-platform (20250814.1-r0) (225/360) Purging abseil-cpp-time (20250814.1-r0) (226/360) Purging abseil-cpp-strings (20250814.1-r0) (227/360) Purging abseil-cpp-strings-internal (20250814.1-r0) (228/360) Purging abseil-cpp-raw-logging-internal (20250814.1-r0) (229/360) Purging abseil-cpp-spinlock-wait (20250814.1-r0) (230/360) Purging abseil-cpp-strerror (20250814.1-r0) (231/360) Purging abseil-cpp-symbolize (20250814.1-r0) (232/360) Purging abseil-cpp-throw-delegate (20250814.1-r0) (233/360) Purging abseil-cpp-time-zone (20250814.1-r0) (234/360) Purging abseil-cpp-tracing-internal (20250814.1-r0) (235/360) Purging abseil-cpp-utf8-for-code-point (20250814.1-r0) (236/360) Purging aom-dev (3.13.1-r1) (237/360) Purging aom (3.13.1-r1) (238/360) Purging aom-libs (3.13.1-r1) (239/360) Purging at-spi2-core-libs (2.58.3-r0) (240/360) Purging cups-libs (2.4.16-r0) (241/360) Purging avahi-libs (0.8-r23) (242/360) Purging boost1.84-filesystem (1.84.0-r5) (243/360) Purging graphite2-dev (1.3.14-r6) (244/360) Purging cairo-dev (1.18.4-r1) (245/360) Purging cairo-tools (1.18.4-r1) (246/360) Purging cairo-gobject (1.18.4-r1) (247/360) Purging cairo (1.18.4-r1) (248/360) Purging fontconfig-dev (2.17.1-r0) (249/360) Purging freetype-dev (2.14.1-r1) (250/360) Purging brotli-dev (1.2.0-r0) (251/360) Purging brotli (1.2.0-r0) (252/360) Purging glib-dev (2.86.3-r1) (253/360) Purging bzip2-dev (1.0.8-r6) (254/360) Purging docbook-xsl (1.79.2-r13) (255/360) Purging docbook-xsl-ns (1.79.2-r13) Executing docbook-xsl-ns-1.79.2-r13.pre-deinstall (256/360) Purging docbook-xsl-nons (1.79.2-r13) Executing docbook-xsl-nons-1.79.2-r13.pre-deinstall (257/360) Purging docbook-xml (4.5-r10) Executing docbook-xml-4.5-r10.pre-deinstall (258/360) Purging gettext-dev (0.24.1-r1) (259/360) Purging xz (5.8.2-r0) (260/360) Purging gettext-asprintf (0.24.1-r1) (261/360) Purging gettext (0.24.1-r1) (262/360) Purging gettext-envsubst (0.24.1-r1) (263/360) Purging libxml2-utils (2.13.9-r0) (264/360) Purging libxslt (1.1.43-r3) (265/360) Purging py3-packaging (25.0-r0) (266/360) Purging py3-parsing (3.3.2-r0) (267/360) Purging pcre2-dev (10.47-r0) (268/360) Purging libpcre2-16 (10.47-r0) (269/360) Purging libpcre2-32 (10.47-r0) (270/360) Purging libedit-dev (20251016.3.1-r1) (271/360) Purging ncurses-dev (6.6_p20251231-r0) (272/360) Purging libncurses++ (6.6_p20251231-r0) (273/360) Purging bsd-compat-headers (0.7.2-r6) (274/360) Purging gdk-pixbuf (2.44.5-r0) Executing gdk-pixbuf-2.44.5-r0.pre-deinstall (275/360) Purging shared-mime-info (2.4-r7) Executing shared-mime-info-2.4-r7.post-deinstall (276/360) Purging libglycin (2.0.7-r1) (277/360) Purging bubblewrap (0.11.0-r3) (278/360) Purging dav1d-dev (1.5.3-r0) (279/360) Purging libdav1d (1.5.3-r0) (280/360) Purging dbus-libs (1.16.2-r1) (281/360) Purging expat-dev (2.7.4-r0) (282/360) Purging expat (2.7.4-r0) (283/360) Purging libxft (2.3.9-r0) (284/360) Purging fontconfig (2.17.1-r0) (285/360) Purging harfbuzz (12.2.0-r1) (286/360) Purging freetype (2.14.1-r1) (287/360) Purging fribidi (1.0.16-r3) (288/360) Purging libxrender-dev (0.9.12-r0) (289/360) Purging libxrender (0.9.12-r0) (290/360) Purging libxext-dev (1.3.7-r0) (291/360) Purging libx11-dev (1.8.13-r0) (292/360) Purging xtrans (1.6.0-r0) (293/360) Purging libxcb-dev (1.17.0-r1) (294/360) Purging xcb-proto (1.17.0-r0) (295/360) Purging python3 (3.12.12-r0) (296/360) Purging gdbm (1.26-r0) (297/360) Purging gettext-libs (0.24.1-r1) (298/360) Purging libatk-1.0 (2.58.3-r0) (299/360) Purging glib (2.86.3-r1) (300/360) Purging gnutls (3.8.11-r0) (301/360) Purging graphite2 (1.3.14-r6) (302/360) Purging icu (78.1-r0) (303/360) Purging icu-libs (78.1-r0) (304/360) Purging icu-data-en (78.1-r0) (305/360) Purging lcms2 (2.17-r0) (306/360) Purging util-linux-dev (2.41.3-r0) (307/360) Purging libfdisk (2.41.3-r0) (308/360) Purging liblastlog2 (2.41.3-r0) (309/360) Purging libmount (2.41.3-r0) (310/360) Purging libsmartcols (2.41.3-r0) (311/360) Purging libblkid (2.41.3-r0) (312/360) Purging libxdmcp-dev (1.1.5-r1) (313/360) Purging libxi (1.8.2-r0) (314/360) Purging libxext (1.3.7-r0) (315/360) Purging libx11 (1.8.13-r0) (316/360) Purging libxcb (1.17.0-r1) (317/360) Purging libxdmcp (1.1.5-r1) (318/360) Purging libbsd (0.12.2-r0) (319/360) Purging libbz2 (1.0.8-r6) (320/360) Purging libeconf (0.8.3-r0) (321/360) Purging libffi-dev (3.5.2-r0) (322/360) Purging linux-headers (6.18.9-r0) (323/360) Purging wayland-libs-client (1.24.0-r0) (324/360) Purging p11-kit (0.25.5-r2) (325/360) Purging libffi (3.5.2-r0) (326/360) Purging libformw (6.6_p20251231-r0) (327/360) Purging libsm (1.2.6-r0) (328/360) Purging libice (1.1.2-r0) (329/360) Purging libintl (0.24.1-r1) (330/360) Purging libjpeg-turbo-dev (3.1.3-r0) (331/360) Purging libturbojpeg (3.1.3-r0) (332/360) Purging tiff (4.7.1-r0) (333/360) Purging libjpeg-turbo (3.1.3-r0) (334/360) Purging libmd (1.1.0-r0) (335/360) Purging libmenuw (6.6_p20251231-r0) (336/360) Purging libpanelw (6.6_p20251231-r0) (337/360) Purging libpng-dev (1.6.54-r0) (338/360) Purging libpng (1.6.54-r0) (339/360) Purging libseccomp (2.6.0-r1) (340/360) Purging libwebp-dev (1.6.0-r0) (341/360) Purging libwebpdecoder (1.6.0-r0) (342/360) Purging libwebpdemux (1.6.0-r0) (343/360) Purging libwebpmux (1.6.0-r0) (344/360) Purging libwebp (1.6.0-r0) (345/360) Purging libsharpyuv (1.6.0-r0) (346/360) Purging libtasn1 (4.21.0-r0) (347/360) Purging libuuid (2.41.3-r0) (348/360) Purging libxau-dev (1.0.12-r0) (349/360) Purging libxau (1.0.12-r0) (350/360) Purging libxml2 (2.13.9-r0) (351/360) Purging mpdecimal (4.0.1-r0) (352/360) Purging nettle (3.10.2-r0) (353/360) Purging pixman-dev (0.46.4-r0) (354/360) Purging pixman (0.46.4-r0) (355/360) Purging sqlite-dev (3.51.2-r1) (356/360) Purging sqlite-libs (3.51.2-r1) (357/360) Purging sqlite (3.51.2-r1) (358/360) Purging xorgproto (2025.1-r0) (359/360) Purging xz-libs (5.8.2-r0) (360/360) Purging zlib-dev (1.3.1-r2) Executing busybox-1.37.0-r31.trigger OK: 441.3 MiB in 107 packages >>> yosys: Updating the testing/x86_64 repository index... >>> yosys: Signing the index...